ispLEVER Classic 1.5.00.05.39.l1 Fitter Report File

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Project Name : dheval_v200 Project Path : C:\Users\sgonzo.DH\Documents\test Project Fitted on : Mon Jul 09 12:07:51 2012 Device : M4128_96 Package : 144 GLB Input Mux Size : 19 Available Blocks : 8 Speed : -7.5 Part Number : LC4128V-75T144I Source Format : Pure_VHDL Project 'dheval_v200' Fit Successfully! Compilation_Times
Prefit Time 0 secs Load Design Time 0.05 secs Partition Time 0.00 secs Place Time 0.00 secs Route Time 0.00 secs Total Fit Time 00:00:01 Design_Summary
Total Input Pins 1 Total Logic Functions 1 Total Output Pins 1 Total Bidir I/O Pins 0 Total Buried Nodes 0 Total Flip-Flops 0 Total D Flip-Flops 0 Total T Flip-Flops 0 Total Latches 0 Total Product Terms 1 Total Reserved Pins 0 Total Locked Pins 2 Total Locked Nodes 0 Total Unique Output Enables 0 Total Unique Clocks 0 Total Unique Clock Enables 0 Total Unique Resets 0 Total Unique Presets 0 Fmax Logic Levels - Device_Resource_Summary
Device Total Used Not Used Utilization ----------------------------------------------------------------------- Dedicated Pins Clock/Input Pins 4 0 4 --> 0 I/O / Enable Pins 2 0 2 --> 0 I/O Pins 94 2 92 --> 2 Logic Functions 128 1 127 --> 0 Input Registers 96 0 96 --> 0 GLB Inputs 288 1 287 --> 0 Logical Product Terms 640 1 639 --> 0 Occupied GLBs 8 1 7 --> 12 Macrocells 128 1 127 --> 0 Control Product Terms: GLB Clock/Clock Enables 8 0 8 --> 0 GLB Reset/Presets 8 0 8 --> 0 Macrocell Clocks 128 0 128 --> 0 Macrocell Clock Enables 128 0 128 --> 0 Macrocell Enables 128 0 128 --> 0 Macrocell Resets 128 0 128 --> 0 Macrocell Presets 128 0 128 --> 0 Global Routing Pool 252 1 251 --> 0 GRP from IFB .. 1 .. --> .. (from input signals) .. 1 .. --> .. (from output signals) .. 0 .. --> .. (from bidir signals) .. 0 .. --> .. GRP from MFB .. 0 .. --> .. ---------------------------------------------------------------------- <Note> 1 : The available PT is the product term that has not been used. <Note> 2 : IFB is I/O feedback. <Note> 3 : MFB is macrocell feedback. GLB_Resource_Summary
# of PT --- Fanin --- I/O Input Macrocells Macrocells Logic clusters Unique Shared Total Pins Regs Used Inaccessible available PTs used ------------------------------------------------------------------------------------------- Maximum GLB 36 *(1) 8 -- -- 16 80 16 ------------------------------------------------------------------------------------------- GLB A 1 0 1 2/12 0 1 0 15 1 1 GLB B 0 0 0 0/12 0 0 0 16 0 0 GLB C 0 0 0 0/12 0 0 0 16 0 0 GLB D 0 0 0 0/12 0 0 0 16 0 0 ------------------------------------------------------------------------------------------- GLB E 0 0 0 0/12 0 0 0 16 0 0 GLB F 0 0 0 0/12 0 0 0 16 0 0 GLB G 0 0 0 0/12 0 0 0 16 0 0 GLB H 0 0 0 0/12 0 0 0 16 0 0 ------------------------------------------------------------------------------------------- TOTALS: 1 0 1 2/96 0 1 0 127 1 1 <Note> 1 : For ispMACH 4000 devices, the number of IOs depends on the GLB. <Note> 2 : Four rightmost columns above reflect last status of the placement process. GLB_Control_Summary
Shared Shared | Mcell Mcell Mcell Mcell Mcell Clk/CE Rst/Pr | Clock CE Enable Reset Preset ------------------------------------------------------------------------------ Maximum GLB 1 1 16 16 16 16 16 ============================================================================== GLB A 0 0 0 0 0 0 0 GLB B 0 0 0 0 0 0 0 GLB C 0 0 0 0 0 0 0 GLB D 0 0 0 0 0 0 0 ------------------------------------------------------------------------------ GLB E 0 0 0 0 0 0 0 GLB F 0 0 0 0 0 0 0 GLB G 0 0 0 0 0 0 0 GLB H 0 0 0 0 0 0 0 ------------------------------------------------------------------------------ <Note> 1 : For ispMACH 4000 devices, the number of output enables depends on the GLB. Optimizer_and_Fitter_Options
Pin Assignment : Yes Group Assignment : No Pin Reservation : No @Ignore_Project_Constraints : Pin Assignments : No Keep Block Assignment -- Keep Segment Assignment -- Group Assignments : No Macrocell Assignment : No Keep Block Assignment -- Keep Segment Assignment -- @Backannotate_Project_Constraints Pin Assignments : No Pin And Block Assignments : No Pin, Macrocell and Block : No @Timing_Constraints : No @Global_Project_Optimization : Balanced Partitioning : Yes Spread Placement : Yes Note : Pack Design : Balanced Partitioning = No Spread Placement = No Spread Design : Balanced Partitioning = Yes Spread Placement = Yes @Logic_Synthesis : Logic Reduction : Yes Node Collapsing : FMAX Fmax_Logic_Level : 1 D/T Synthesis : Yes XOR Synthesis : Yes Max. P-Term for Collapsing : 16 Max. P-Term for Splitting : 80 Max Symbols : 24 @Utilization_options Max. % of Macrocells used : 100 @Usercode (HEX) @IO_Types Default = LVCMOS18 (2) @Output_Slew_Rate Default = FAST (2) @Power Default = HIGH (2) @Pull Default = PULLUP_UP (2) @Fast_Bypass Default = None (2) @ORP_Bypass Default = None @Input_Registers Default = None (2) @Register_Powerup Default = None Device Options: <Note> 1 : Reserved unused I/Os can be independently driven to Low or High, and does not follow the drive level set for the Global Configure Unused I/O Option. <Note> 2 : For user-specified constraints on individual signals, refer to the Output, Bidir and Buried Signal Lists. Pinout_Listing
| Pin | Bank |GLB |Assigned| | Signal| Pin No| Type |Number|Pad |Pin | I/O Type | Type | Signal name -------------------------------------------------------------------------- 1 | GND | - | | | | | 2 | TDI | - | | | | | 3 |VCCIO0 | - | | | | | 4 | I_O | 0 |B0 | | | | 5 | I_O | 0 |B1 | | | | 6 | I_O | 0 |B2 | | | | 7 | I_O | 0 |B4 | | | | 8 | I_O | 0 |B5 | | | | 9 | I_O | 0 |B6 | | | | 10 |GNDIO0 | - | | | | | 11 | I_O | 0 |B8 | | | | 12 | I_O | 0 |B9 | | | | 13 | I_O | 0 |B10 | | | | 14 | I_O | 0 |B12 | | | | 15 | I_O | 0 |B13 | | | | 16 | I_O | 0 |B14 | | | | 17 | NC | - | | | | | 18 |GNDIO0 | - | | | | | 19 |VCCIO0 | - | | | | | 20 | NC | - | | | | | 21 | I_O | 0 |C14 | | | | 22 | I_O | 0 |C13 | | | | 23 | I_O | 0 |C12 | | | | 24 | I_O | 0 |C10 | | | | 25 | I_O | 0 |C9 | | | | 26 | I_O | 0 |C8 | | | | 27 |GNDIO0 | - | | | | | 28 | I_O | 0 |C6 | | | | 29 | I_O | 0 |C5 | | | | 30 | I_O | 0 |C4 | | | | 31 | I_O | 0 |C2 | | | | 32 | I_O | 0 |C1 | | | | 33 | I_O | 0 |C0 | | | | 34 |VCCIO0 | - | | | | | 35 | TCK | - | | | | | 36 | VCC | - | | | | | 37 | GND | - | | | | | 38 | NC | - | | | | | 39 | I_O | 0 |D14 | | | | 40 | I_O | 0 |D13 | | | | 41 | I_O | 0 |D12 | | | | 42 | I_O | 0 |D10 | | | | 43 | I_O | 0 |D9 | | | | 44 | I_O | 0 |D8 | | | | 45 | NC | - | | | | | 46 |GNDIO0 | - | | | | | 47 |VCCIO0 | - | | | | | 48 | I_O | 0 |D6 | | | | 49 | I_O | 0 |D5 | | | | 50 | I_O | 0 |D4 | | | | 51 | I_O | 0 |D2 | | | | 52 | I_O | 0 |D1 | | | | 53 | I_O | 0 |D0 | | | | 54 |INCLK1 | 0 | | | | | 55 |GNDIO1 | - | | | | | 56 |INCLK2 | 1 | | | | | 57 | VCC | - | | | | | 58 | I_O | 1 |E0 | | | | 59 | I_O | 1 |E1 | | | | 60 | I_O | 1 |E2 | | | | 61 | I_O | 1 |E4 | | | | 62 | I_O | 1 |E5 | | | | 63 | I_O | 1 |E6 | | | | 64 |VCCIO1 | - | | | | | 65 |GNDIO1 | - | | | | | 66 | I_O | 1 |E8 | | | | 67 | I_O | 1 |E9 | | | | 68 | I_O | 1 |E10 | | | | 69 | I_O | 1 |E12 | | | | 70 | I_O | 1 |E13 | | | | 71 | I_O | 1 |E14 | | | | 72 | NC | - | | | | | 73 | GND | - | | | | | 74 | TMS | - | | | | | 75 |VCCIO1 | - | | | | | 76 | I_O | 1 |F0 | | | | 77 | I_O | 1 |F1 | | | | 78 | I_O | 1 |F2 | | | | 79 | I_O | 1 |F4 | | | | 80 | I_O | 1 |F5 | | | | 81 | I_O | 1 |F6 | | | | 82 |GNDIO1 | - | | | | | 83 | I_O | 1 |F8 | | | | 84 | I_O | 1 |F9 | | | | 85 | I_O | 1 |F10 | | | | 86 | I_O | 1 |F12 | | | | 87 | I_O | 1 |F13 | | | | 88 | I_O | 1 |F14 | | | | 89 | NC | - | | | | | 90 |GNDIO1 | - | | | | | 91 |VCCIO1 | - | | | | | 92 | NC | - | | | | | 93 | I_O | 1 |G14 | | | | 94 | I_O | 1 |G13 | | | | 95 | I_O | 1 |G12 | | | | 96 | I_O | 1 |G10 | | | | 97 | I_O | 1 |G9 | | | | 98 | I_O | 1 |G8 | | | | 99 |GNDIO1 | - | | | | | 100 | I_O | 1 |G6 | | | | 101 | I_O | 1 |G5 | | | | 102 | I_O | 1 |G4 | | | | 103 | I_O | 1 |G2 | | | | 104 | I_O | 1 |G1 | | | | 105 | I_O | 1 |G0 | | | | 106 |VCCIO1 | - | | | | | 107 | TDO | - | | | | | 108 | VCC | - | | | | | 109 | GND | - | | | | | 110 | NC | - | | | | | 111 | I_O | 1 |H14 | | | | 112 | I_O | 1 |H13 | | | | 113 | I_O | 1 |H12 | | | | 114 | I_O | 1 |H10 | | | | 115 | I_O | 1 |H9 | | | | 116 | I_O | 1 |H8 | | | | 117 | NC | - | | | | | 118 |GNDIO1 | - | | | | | 119 |VCCIO1 | - | | | | | 120 | I_O | 1 |H6 | | | | 121 | I_O | 1 |H5 | | | | 122 | I_O | 1 |H4 | | | | 123 | I_O | 1 |H2 | | | | 124 | I_O | 1 |H1 | | | | 125 | I_O/OE| 1 |H0 | | | | 126 |INCLK3 | 1 | | | | | 127 |GNDIO0 | - | | | | | 128 |INCLK0 | 0 | | | | | 129 | VCC | - | | | | | 130 | I_O/OE| 0 |A0 | | | | 131 | I_O | 0 |A1 | | | | 132 | I_O | 0 |A2 | | | | 133 | I_O | 0 |A4 | | | | 134 | I_O | 0 |A5 | * |LVCMOS18 | Input |X_VAR1 135 | I_O | 0 |A6 | | | | 136 |VCCIO0 | - | | | | | 137 |GNDIO0 | - | | | | | 138 | I_O | 0 |A8 | | | | 139 | I_O | 0 |A9 | | | | 140 | I_O | 0 |A10 | * |LVCMOS18 | Output|X_PLD_LED 141 | I_O | 0 |A12 | | | | 142 | I_O | 0 |A13 | | | | 143 | I_O | 0 |A14 | | | | 144 | NC | - | | | | | -------------------------------------------------------------------------- <Note> GLB Pad : This notation refers to the GLB I/O pad number in the device. <Note> Assigned Pin : user or dedicated input assignment (E.g. Clock pins). <Note> Pin Type : ClkIn : Dedicated input or clock pin CLK : Dedicated clock pin I_O : Input/Output pin INP : Dedicated input pin JTAG : JTAG Control and test pin NC : No connected Input_Signal_List
Input Pin Fanout Pin GLB Type Pullup Signal ----------------------------------------- 134 A I/O 1 A------- Up X_VAR1 ----------------------------------------- Output_Signal_List
I C P R P O Output N L Mc R E U C O F B Fanout Pin GLB P LL PTs S Type E S P E E P P Slew Pullup Signal -------------------------------------------------------------------------- 140 A 1 1 1 1 COM -------- Fast Up X_PLD_LED -------------------------------------------------------------------------- <Note> CLS = Number of clusters used INP = Number of input signals PTs = Number of product terms LL = Number of logic levels PRE = Has preset equation RES = Has reset equation PUP = Power-Up initial state: R=Reset, S=Set CE = Has clock enable equation OE = Has output enable equation FP = Fast path used OBP = ORP bypass used Bidir_Signal_List
I C P R P O Bidir N L Mc R E U C O F B Fanout Pin GLB P LL PTs S Type E S P E E P P Slew Pullup Signal ----------------------------------------------------------------------- ----------------------------------------------------------------------- <Note> CLS = Number of clusters used INP = Number of input signals PTs = Number of product terms LL = Number of logic levels PRE = Has preset equation RES = Has reset equation PUP = Power-Up initial state: R=Reset, S=Set CE = Has clock enable equation OE = Has output enable equation FP = Fast path used OBP = ORP bypass used Buried_Signal_List
PostFit_Equations
X_PLD_LED = !X_VAR1 ; (1 pterm, 1 signal)