ispLEVER Classic 1.5.00.05.39.l1 Fitter Report File

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Project Name : dheval_v300 Project Path : D:\CPLD_DHEval Project Fitted on : Thu Mar 15 14:52:15 2012 Device : M4128_96 Package : 144 GLB Input Mux Size : 19 Available Blocks : 8 Speed : -7.5 Part Number : LC4128V-75T144I Source Format : Pure_VHDL Project 'dheval_v300' Fit Successfully! Compilation_Times
Prefit Time 0 secs Load Design Time 0.03 secs Partition Time 0.02 secs Place Time 0.00 secs Route Time 0.00 secs Total Fit Time 00:00:01 Design_Summary
Total Input Pins 19 Total Logic Functions 56 Total Output Pins 24 Total Bidir I/O Pins 32 Total Buried Nodes 0 Total Flip-Flops 0 Total D Flip-Flops 0 Total T Flip-Flops 0 Total Latches 0 Total Product Terms 84 Total Reserved Pins 0 Total Locked Pins 75 Total Locked Nodes 0 Total Unique Output Enables 2 Total Unique Clocks 0 Total Unique Clock Enables 0 Total Unique Resets 0 Total Unique Presets 0 Fmax Logic Levels - Device_Resource_Summary
Device Total Used Not Used Utilization ----------------------------------------------------------------------- Dedicated Pins Clock/Input Pins 4 0 4 --> 0 I/O / Enable Pins 2 0 2 --> 0 I/O Pins 94 75 19 --> 79 Logic Functions 128 56 72 --> 43 Input Registers 96 0 96 --> 0 GLB Inputs 288 52 236 --> 18 Logical Product Terms 640 52 588 --> 8 Occupied GLBs 8 8 0 --> 100 Macrocells 128 56 72 --> 43 Control Product Terms: GLB Clock/Clock Enables 8 0 8 --> 0 GLB Reset/Presets 8 0 8 --> 0 Macrocell Clocks 128 0 128 --> 0 Macrocell Clock Enables 128 0 128 --> 0 Macrocell Enables 128 0 128 --> 0 Macrocell Resets 128 0 128 --> 0 Macrocell Presets 128 0 128 --> 0 Global Routing Pool 252 51 201 --> 20 GRP from IFB .. 51 .. --> .. (from input signals) .. 19 .. --> .. (from output signals) .. 0 .. --> .. (from bidir signals) .. 32 .. --> .. GRP from MFB .. 0 .. --> .. ---------------------------------------------------------------------- <Note> 1 : The available PT is the product term that has not been used. <Note> 2 : IFB is I/O feedback. <Note> 3 : MFB is macrocell feedback. GLB_Resource_Summary
# of PT --- Fanin --- I/O Input Macrocells Macrocells Logic clusters Unique Shared Total Pins Regs Used Inaccessible available PTs used ------------------------------------------------------------------------------------------- Maximum GLB 36 *(1) 8 -- -- 16 80 16 ------------------------------------------------------------------------------------------- GLB A 0 0 0 3/12 0 0 0 16 0 0 GLB B 1 0 1 11/12 0 1 0 15 1 1 GLB C 7 0 7 12/12 0 7 0 9 7 7 GLB D 8 0 8 10/12 0 9 0 7 9 9 ------------------------------------------------------------------------------------------- GLB E 13 0 13 12/12 0 12 0 4 12 12 GLB F 12 0 12 12/12 0 12 0 4 12 12 GLB G 9 0 9 12/12 0 12 0 4 9 12 GLB H 2 0 2 3/12 0 3 0 13 2 3 ------------------------------------------------------------------------------------------- TOTALS: 52 0 52 75/96 0 56 0 72 52 56 <Note> 1 : For ispMACH 4000 devices, the number of IOs depends on the GLB. <Note> 2 : Four rightmost columns above reflect last status of the placement process. GLB_Control_Summary
Shared Shared | Mcell Mcell Mcell Mcell Mcell Clk/CE Rst/Pr | Clock CE Enable Reset Preset ------------------------------------------------------------------------------ Maximum GLB 1 1 16 16 16 16 16 ============================================================================== GLB A 0 0 0 0 0 0 0 GLB B 0 0 0 0 0 0 0 GLB C 0 0 0 0 0 0 0 GLB D 0 0 0 0 0 0 0 ------------------------------------------------------------------------------ GLB E 0 0 0 0 0 0 0 GLB F 0 0 0 0 0 0 0 GLB G 0 0 0 0 0 0 0 GLB H 0 0 0 0 0 0 0 ------------------------------------------------------------------------------ <Note> 1 : For ispMACH 4000 devices, the number of output enables depends on the GLB. Optimizer_and_Fitter_Options
Pin Assignment : Yes Group Assignment : No Pin Reservation : No @Ignore_Project_Constraints : Pin Assignments : No Keep Block Assignment -- Keep Segment Assignment -- Group Assignments : No Macrocell Assignment : No Keep Block Assignment -- Keep Segment Assignment -- @Backannotate_Project_Constraints Pin Assignments : No Pin And Block Assignments : No Pin, Macrocell and Block : No @Timing_Constraints : No @Global_Project_Optimization : Balanced Partitioning : Yes Spread Placement : Yes Note : Pack Design : Balanced Partitioning = No Spread Placement = No Spread Design : Balanced Partitioning = Yes Spread Placement = Yes @Logic_Synthesis : Logic Reduction : Yes Node Collapsing : FMAX Fmax_Logic_Level : 1 D/T Synthesis : Yes XOR Synthesis : Yes Max. P-Term for Collapsing : 16 Max. P-Term for Splitting : 80 Max Symbols : 24 @Utilization_options Max. % of Macrocells used : 100 @Usercode (HEX) @IO_Types Default = LVCMOS18 (2) @Output_Slew_Rate Default = FAST (2) @Power Default = HIGH (2) @Pull Default = PULLUP_UP (2) @Fast_Bypass Default = None (2) @ORP_Bypass Default = None @Input_Registers Default = None (2) @Register_Powerup Default = None Device Options: <Note> 1 : Reserved unused I/Os can be independently driven to Low or High, and does not follow the drive level set for the Global Configure Unused I/O Option. <Note> 2 : For user-specified constraints on individual signals, refer to the Output, Bidir and Buried Signal Lists. Pinout_Listing
| Pin | Bank |GLB |Assigned| | Signal| Pin No| Type |Number|Pad |Pin | I/O Type | Type | Signal name ------------------------------------------------------------------------------- 1 | GND | - | | | | | 2 | TDI | - | | | | | 3 |VCCIO0 | - | | | | | 4 | I_O | 0 |B0 | * |LVCMOS33 | Input |X_IMX_ADR_0_ 5 | I_O | 0 |B1 | * |LVCMOS33 | Input |X_IMX_ADR_1_ 6 | I_O | 0 |B2 | * |LVCMOS33 | Input |X_IMX_ADR_2_ 7 | I_O | 0 |B4 | * |LVCMOS33 | Input |X_IMX_ADR_3_ 8 | I_O | 0 |B5 | * |LVCMOS33 | Input |X_IMX_ADR_4_ 9 | I_O | 0 |B6 | * |LVCMOS33 | Input |X_IMX_ADR_5_ 10 |GNDIO0 | - | | | | | 11 | I_O | 0 |B8 | * |LVCMOS33 | Input |X_IMX_ADR_6_ 12 | I_O | 0 |B9 | * |LVCMOS33 | Input |X_IMX_ADR_7_ 13 | I_O | 0 |B10 | * |LVCMOS33 | Input |X_IMX_nCS 14 | I_O | 0 |B12 | | | | 15 | I_O | 0 |B13 | * |LVCMOS33 | Input |X_IMX_nWE 16 | I_O | 0 |B14 | * |LVCMOS33 | Bidir |X_IMX_DAT_0_ 17 | NC | - | | | | | 18 |GNDIO0 | - | | | | | 19 |VCCIO0 | - | | | | | 20 | NC | - | | | | | 21 | I_O | 0 |C14 | * |LVCMOS33 | Bidir |X_IMX_DAT_1_ 22 | I_O | 0 |C13 | * |LVCMOS33 | Bidir |X_IMX_DAT_2_ 23 | I_O | 0 |C12 | * |LVCMOS33 | Bidir |X_IMX_DAT_3_ 24 | I_O | 0 |C10 | * |LVCMOS33 | Bidir |X_IMX_DAT_4_ 25 | I_O | 0 |C9 | * |LVCMOS33 | Bidir |X_IMX_DAT_5_ 26 | I_O | 0 |C8 | * |LVCMOS33 | Bidir |X_IMX_DAT_6_ 27 |GNDIO0 | - | | | | | 28 | I_O | 0 |C6 | * |LVCMOS33 | Bidir |X_IMX_DAT_7_ 29 | I_O | 0 |C5 | * |LVCMOS33 | Input |X_IMX_ADR_11_ 30 | I_O | 0 |C4 | * |LVCMOS33 | Input |X_IMX_ADR_12_ 31 | I_O | 0 |C2 | * |LVCMOS33 | Input |X_IMX_ADR_13_ 32 | I_O | 0 |C1 | * |LVCMOS33 | Input |X_IMX_ADR_14_ 33 | I_O | 0 |C0 | * |LVCMOS33 | Input |X_IMX_ADR_15_ 34 |VCCIO0 | - | | | | | 35 | TCK | - | | | | | 36 | VCC | - | | | | | 37 | GND | - | | | | | 38 | NC | - | | | | | 39 | I_O | 0 |D14 | | | | 40 | I_O | 0 |D13 | | | | 41 | I_O | 0 |D12 | * |LVCMOS33 | Input |X_IMX_nOE 42 | I_O | 0 |D10 | * |LVCMOS33 | Bidir |X_IMX_DAT_8_ 43 | I_O | 0 |D9 | * |LVCMOS33 | Bidir |X_IMX_DAT_9_ 44 | I_O | 0 |D8 | * |LVCMOS33 | Bidir |X_IMX_DAT_10_ 45 | NC | - | | | | | 46 |GNDIO0 | - | | | | | 47 |VCCIO0 | - | | | | | 48 | I_O | 0 |D6 | * |LVCMOS33 | Bidir |X_IMX_DAT_11_ 49 | I_O | 0 |D5 | * |LVCMOS33 | Bidir |X_IMX_DAT_12_ 50 | I_O | 0 |D4 | * |LVCMOS33 | Bidir |X_IMX_DAT_13_ 51 | I_O | 0 |D2 | * |LVCMOS33 | Bidir |X_IMX_DAT_14_ 52 | I_O | 0 |D1 | * |LVCMOS33 | Bidir |X_IMX_DAT_15_ 53 | I_O | 0 |D0 | * |LVCMOS33 | Output|X_PLD_LED 54 |INCLK1 | 0 | | | | | 55 |GNDIO1 | - | | | | | 56 |INCLK2 | 1 | | | | | 57 | VCC | - | | | | | 58 | I_O | 1 |E0 | * |LVCMOS33 | Output|X_RAM_ADR_10_ 59 | I_O | 1 |E1 | * |LVCMOS33 | Output|X_RAM_ADR_9_ 60 | I_O | 1 |E2 | * |LVCMOS33 | Output|X_RAM_ADR_11_ 61 | I_O | 1 |E4 | * |LVCMOS33 | Output|X_RAM_ADR_8_ 62 | I_O | 1 |E5 | * |LVCMOS33 | Output|X_RAM_ADR_12_ 63 | I_O | 1 |E6 | * |LVCMOS33 | Output|X_RAM_ADR_7_ 64 |VCCIO1 | - | | | | | 65 |GNDIO1 | - | | | | | 66 | I_O | 1 |E8 | * |LVCMOS33 | Output|X_RAM_ADR_13_ 67 | I_O | 1 |E9 | * |LVCMOS33 | Output|X_RAM_ADR_6_ 68 | I_O | 1 |E10 | * |LVCMOS33 | Output|X_RAM_ADR_14_ 69 | I_O | 1 |E12 | * |LVCMOS33 | Output|X_RAM_ADR_5_ 70 | I_O | 1 |E13 | * |LVCMOS33 | Bidir |X_RAM_DAT_8_ 71 | I_O | 1 |E14 | * |LVCMOS33 | Output|X_RAM_nWE 72 | NC | - | | | | | 73 | GND | - | | | | | 74 | TMS | - | | | | | 75 |VCCIO1 | - | | | | | 76 | I_O | 1 |F0 | * |LVCMOS33 | Bidir |X_RAM_DAT_9_ 77 | I_O | 1 |F1 | * |LVCMOS33 | Bidir |X_RAM_DAT_7_ 78 | I_O | 1 |F2 | * |LVCMOS33 | Bidir |X_RAM_DAT_10_ 79 | I_O | 1 |F4 | * |LVCMOS33 | Bidir |X_RAM_DAT_6_ 80 | I_O | 1 |F5 | * |LVCMOS33 | Bidir |X_RAM_DAT_11_ 81 | I_O | 1 |F6 | * |LVCMOS33 | Bidir |X_RAM_DAT_5_ 82 |GNDIO1 | - | | | | | 83 | I_O | 1 |F8 | * |LVCMOS33 | Bidir |X_RAM_DAT_12_ 84 | I_O | 1 |F9 | * |LVCMOS33 | Bidir |X_RAM_DAT_4_ 85 | I_O | 1 |F10 | * |LVCMOS33 | Bidir |X_RAM_DAT_13_ 86 | I_O | 1 |F12 | * |LVCMOS33 | Bidir |X_RAM_DAT_3_ 87 | I_O | 1 |F13 | * |LVCMOS33 | Bidir |X_RAM_DAT_14_ 88 | I_O | 1 |F14 | * |LVCMOS33 | Bidir |X_RAM_DAT_2_ 89 | NC | - | | | | | 90 |GNDIO1 | - | | | | | 91 |VCCIO1 | - | | | | | 92 | NC | - | | | | | 93 | I_O | 1 |G14 | * |LVCMOS33 | Bidir |X_RAM_DAT_15_ 94 | I_O | 1 |G13 | * |LVCMOS33 | Bidir |X_RAM_DAT_1_ 95 | I_O | 1 |G12 | * |LVCMOS33 | Output|X_RAM_nLB 96 | I_O | 1 |G10 | * |LVCMOS33 | Bidir |X_RAM_DAT_0_ 97 | I_O | 1 |G9 | * |LVCMOS33 | Output|X_RAM_nUB 98 | I_O | 1 |G8 | * |LVCMOS33 | Output|X_RAM_nCS 99 |GNDIO1 | - | | | | | 100 | I_O | 1 |G6 | * |LVCMOS33 | Output|X_RAM_nOE 101 | I_O | 1 |G5 | * |LVCMOS33 | Output|X_RAM_ADR_4_ 102 | I_O | 1 |G4 | * |LVCMOS33 | Output|X_RAM_ADR_15_ 103 | I_O | 1 |G2 | * |LVCMOS33 | Output|X_RAM_ADR_3_ 104 | I_O | 1 |G1 | * |LVCMOS33 | Output|X_RAM_ADR_16_ 105 | I_O | 1 |G0 | * |LVCMOS33 | Output|X_RAM_ADR_2_ 106 |VCCIO1 | - | | | | | 107 | TDO | - | | | | | 108 | VCC | - | | | | | 109 | GND | - | | | | | 110 | NC | - | | | | | 111 | I_O | 1 |H14 | * |LVCMOS33 | Output|X_RAM_ADR_17_ 112 | I_O | 1 |H13 | * |LVCMOS33 | Output|X_RAM_ADR_1_ 113 | I_O | 1 |H12 | | | | 114 | I_O | 1 |H10 | * |LVCMOS33 | Output|X_RAM_ADR_0_ 115 | I_O | 1 |H9 | | | | 116 | I_O | 1 |H8 | | | | 117 | NC | - | | | | | 118 |GNDIO1 | - | | | | | 119 |VCCIO1 | - | | | | | 120 | I_O | 1 |H6 | | | | 121 | I_O | 1 |H5 | | | | 122 | I_O | 1 |H4 | | | | 123 | I_O | 1 |H2 | | | | 124 | I_O | 1 |H1 | | | | 125 | I_O/OE| 1 |H0 | | | | 126 |INCLK3 | 1 | | | | | 127 |GNDIO0 | - | | | | | 128 |INCLK0 | 0 | | | | | 129 | VCC | - | | | | | 130 | I_O/OE| 0 |A0 | | | | 131 | I_O | 0 |A1 | | | | 132 | I_O | 0 |A2 | | | | 133 | I_O | 0 |A4 | | | | 134 | I_O | 0 |A5 | | | | 135 | I_O | 0 |A6 | * |LVCMOS33 | Input |X_IMX_ADR_8_ 136 |VCCIO0 | - | | | | | 137 |GNDIO0 | - | | | | | 138 | I_O | 0 |A8 | * |LVCMOS33 | Input |X_IMX_ADR_9_ 139 | I_O | 0 |A9 | * |LVCMOS33 | Input |X_IMX_ADR_10_ 140 | I_O | 0 |A10 | | | | 141 | I_O | 0 |A12 | | | | 142 | I_O | 0 |A13 | | | | 143 | I_O | 0 |A14 | | | | 144 | NC | - | | | | | ------------------------------------------------------------------------------- <Note> GLB Pad : This notation refers to the GLB I/O pad number in the device. <Note> Assigned Pin : user or dedicated input assignment (E.g. Clock pins). <Note> Pin Type : ClkIn : Dedicated input or clock pin CLK : Dedicated clock pin I_O : Input/Output pin INP : Dedicated input pin JTAG : JTAG Control and test pin NC : No connected Input_Signal_List
Input Pin Fanout Pin GLB Type Pullup Signal ------------------------------------------------ 4 B I/O 1 -------H Up X_IMX_ADR_0_ 139 A I/O 1 ----E--- Up X_IMX_ADR_10_ 29 C I/O 1 ----E--- Up X_IMX_ADR_11_ 30 C I/O 1 ----E--- Up X_IMX_ADR_12_ 31 C I/O 1 ----E--- Up X_IMX_ADR_13_ 32 C I/O 1 ----E--- Up X_IMX_ADR_14_ 33 C I/O 1 ------G- Up X_IMX_ADR_15_ 5 B I/O 1 -------H Up X_IMX_ADR_1_ 6 B I/O 1 ------G- Up X_IMX_ADR_2_ 7 B I/O 1 ------G- Up X_IMX_ADR_3_ 8 B I/O 1 ------G- Up X_IMX_ADR_4_ 9 B I/O 1 ----E--- Up X_IMX_ADR_5_ 11 B I/O 1 ----E--- Up X_IMX_ADR_6_ 12 B I/O 1 ----E--- Up X_IMX_ADR_7_ 135 A I/O 1 ----E--- Up X_IMX_ADR_8_ 138 A I/O 1 ----E--- Up X_IMX_ADR_9_ 13 B I/O 2 ----E-G- Up X_IMX_nCS 41 D I/O 1 ------G- Up X_IMX_nOE 15 B I/O 1 ----E--- Up X_IMX_nWE ------------------------------------------------ Output_Signal_List
I C P R P O Output N L Mc R E U C O F B Fanout Pin GLB P LL PTs S Type E S P E E P P Slew Pullup Signal ------------------------------------------------------------------------------ 53 D 0 - 1 1 COM -------- Fast Up X_PLD_LED 114 H 1 1 1 1 COM -------- Fast Up X_RAM_ADR_0_ 58 E 1 1 1 1 COM -------- Fast Up X_RAM_ADR_10_ 60 E 1 1 1 1 COM -------- Fast Up X_RAM_ADR_11_ 62 E 1 1 1 1 COM -------- Fast Up X_RAM_ADR_12_ 66 E 1 1 1 1 COM -------- Fast Up X_RAM_ADR_13_ 68 E 1 1 1 1 COM -------- Fast Up X_RAM_ADR_14_ 102 G 1 1 1 1 COM -------- Fast Up X_RAM_ADR_15_ 104 G 0 - 0 1 COM -------- Fast Up X_RAM_ADR_16_ 111 H 0 - 0 1 COM -------- Fast Up X_RAM_ADR_17_ 112 H 1 1 1 1 COM -------- Fast Up X_RAM_ADR_1_ 105 G 1 1 1 1 COM -------- Fast Up X_RAM_ADR_2_ 103 G 1 1 1 1 COM -------- Fast Up X_RAM_ADR_3_ 101 G 1 1 1 1 COM -------- Fast Up X_RAM_ADR_4_ 69 E 1 1 1 1 COM -------- Fast Up X_RAM_ADR_5_ 67 E 1 1 1 1 COM -------- Fast Up X_RAM_ADR_6_ 63 E 1 1 1 1 COM -------- Fast Up X_RAM_ADR_7_ 61 E 1 1 1 1 COM -------- Fast Up X_RAM_ADR_8_ 59 E 1 1 1 1 COM -------- Fast Up X_RAM_ADR_9_ 98 G 1 1 1 1 COM -------- Fast Up X_RAM_nCS 95 G 0 - 0 1 COM -------- Fast Up X_RAM_nLB 100 G 1 1 1 1 COM -------- Fast Up X_RAM_nOE 97 G 0 - 0 1 COM -------- Fast Up X_RAM_nUB 71 E 1 1 1 1 COM -------- Fast Up X_RAM_nWE ------------------------------------------------------------------------------ <Note> CLS = Number of clusters used INP = Number of input signals PTs = Number of product terms LL = Number of logic levels PRE = Has preset equation RES = Has reset equation PUP = Power-Up initial state: R=Reset, S=Set CE = Has clock enable equation OE = Has output enable equation FP = Fast path used OBP = ORP bypass used Bidir_Signal_List
I C P R P O Bidir N L Mc R E U C O F B Fanout Pin GLB P LL PTs S Type E S P E E P P Slew Pullup Signal ------------------------------------------------------------------------------ 16 B 1 1 1 1 COM * 1 ------G- Fast Up X_IMX_DAT_0_ 44 D 1 1 1 1 COM * 1 -----F-- Fast Up X_IMX_DAT_10_ 48 D 1 1 1 1 COM * 1 -----F-- Fast Up X_IMX_DAT_11_ 49 D 1 1 1 1 COM * 1 -----F-- Fast Up X_IMX_DAT_12_ 50 D 1 1 1 1 COM * 1 -----F-- Fast Up X_IMX_DAT_13_ 51 D 1 1 1 1 COM * 1 -----F-- Fast Up X_IMX_DAT_14_ 52 D 1 1 1 1 COM * 1 ------G- Fast Up X_IMX_DAT_15_ 21 C 1 1 1 1 COM * 1 ------G- Fast Up X_IMX_DAT_1_ 22 C 1 1 1 1 COM * 1 -----F-- Fast Up X_IMX_DAT_2_ 23 C 1 1 1 1 COM * 1 -----F-- Fast Up X_IMX_DAT_3_ 24 C 1 1 1 1 COM * 1 -----F-- Fast Up X_IMX_DAT_4_ 25 C 1 1 1 1 COM * 1 -----F-- Fast Up X_IMX_DAT_5_ 26 C 1 1 1 1 COM * 1 -----F-- Fast Up X_IMX_DAT_6_ 28 C 1 1 1 1 COM * 1 -----F-- Fast Up X_IMX_DAT_7_ 42 D 1 1 1 1 COM * 1 ----E--- Fast Up X_IMX_DAT_8_ 43 D 1 1 1 1 COM * 1 -----F-- Fast Up X_IMX_DAT_9_ 96 G 1 1 1 1 COM * 1 -B------ Fast Up X_RAM_DAT_0_ 78 F 1 1 1 1 COM * 1 ---D---- Fast Up X_RAM_DAT_10_ 80 F 1 1 1 1 COM * 1 ---D---- Fast Up X_RAM_DAT_11_ 83 F 1 1 1 1 COM * 1 ---D---- Fast Up X_RAM_DAT_12_ 85 F 1 1 1 1 COM * 1 ---D---- Fast Up X_RAM_DAT_13_ 87 F 1 1 1 1 COM * 1 ---D---- Fast Up X_RAM_DAT_14_ 93 G 1 1 1 1 COM * 1 ---D---- Fast Up X_RAM_DAT_15_ 94 G 1 1 1 1 COM * 1 --C----- Fast Up X_RAM_DAT_1_ 88 F 1 1 1 1 COM * 1 --C----- Fast Up X_RAM_DAT_2_ 86 F 1 1 1 1 COM * 1 --C----- Fast Up X_RAM_DAT_3_ 84 F 1 1 1 1 COM * 1 --C----- Fast Up X_RAM_DAT_4_ 81 F 1 1 1 1 COM * 1 --C----- Fast Up X_RAM_DAT_5_ 79 F 1 1 1 1 COM * 1 --C----- Fast Up X_RAM_DAT_6_ 77 F 1 1 1 1 COM * 1 --C----- Fast Up X_RAM_DAT_7_ 70 E 1 1 1 1 COM * 1 ---D---- Fast Up X_RAM_DAT_8_ 76 F 1 1 1 1 COM * 1 ---D---- Fast Up X_RAM_DAT_9_ ------------------------------------------------------------------------------ <Note> CLS = Number of clusters used INP = Number of input signals PTs = Number of product terms LL = Number of logic levels PRE = Has preset equation RES = Has reset equation PUP = Power-Up initial state: R=Reset, S=Set CE = Has clock enable equation OE = Has output enable equation FP = Fast path used OBP = ORP bypass used Buried_Signal_List
I C P R P Node N L Mc R E U C I F Fanout Mc GLB P LL PTs S Type E S P E R P Signal ---------------------------------------------------------------- -- G 2 1 0 PTOE -------- X_IMX_DAT_3_.OE -- E 2 1 0 PTOE -------- X_RAM_DAT_0_.OE ---------------------------------------------------------------- <Note> CLS = Number of clusters used INP = Number of input signals PTs = Number of product terms LL = Number of logic levels PRE = Has preset equation RES = Has reset equation PUP = Power-Up initial state: R=Reset, S=Set CE = Has clock enable equation OE = Has output enable equation IR = Input register FP = Fast path used OBP = ORP bypass used PostFit_Equations
X_IMX_DAT_0_ = X_RAM_DAT_0_.PIN ; (1 pterm, 1 signal) X_IMX_DAT_0_.OE = !X_IMX_nOE & !X_IMX_nCS ; (1 pterm, 2 signals) X_IMX_DAT_10_ = X_RAM_DAT_10_.PIN ; (1 pterm, 1 signal) X_IMX_DAT_10_.OE = !X_IMX_nOE & !X_IMX_nCS ; (1 pterm, 2 signals) X_IMX_DAT_11_ = X_RAM_DAT_11_.PIN ; (1 pterm, 1 signal) X_IMX_DAT_11_.OE = !X_IMX_nOE & !X_IMX_nCS ; (1 pterm, 2 signals) X_IMX_DAT_12_ = X_RAM_DAT_12_.PIN ; (1 pterm, 1 signal) X_IMX_DAT_12_.OE = !X_IMX_nOE & !X_IMX_nCS ; (1 pterm, 2 signals) X_IMX_DAT_13_ = X_RAM_DAT_13_.PIN ; (1 pterm, 1 signal) X_IMX_DAT_13_.OE = !X_IMX_nOE & !X_IMX_nCS ; (1 pterm, 2 signals) X_IMX_DAT_14_ = X_RAM_DAT_14_.PIN ; (1 pterm, 1 signal) X_IMX_DAT_14_.OE = !X_IMX_nOE & !X_IMX_nCS ; (1 pterm, 2 signals) X_IMX_DAT_15_ = X_RAM_DAT_15_.PIN ; (1 pterm, 1 signal) X_IMX_DAT_15_.OE = !X_IMX_nOE & !X_IMX_nCS ; (1 pterm, 2 signals) X_IMX_DAT_1_ = X_RAM_DAT_1_.PIN ; (1 pterm, 1 signal) X_IMX_DAT_1_.OE = !X_IMX_nOE & !X_IMX_nCS ; (1 pterm, 2 signals) X_IMX_DAT_2_ = X_RAM_DAT_2_.PIN ; (1 pterm, 1 signal) X_IMX_DAT_2_.OE = !X_IMX_nOE & !X_IMX_nCS ; (1 pterm, 2 signals) X_IMX_DAT_3_ = X_RAM_DAT_3_.PIN ; (1 pterm, 1 signal) X_IMX_DAT_3_.OE = !X_IMX_nOE & !X_IMX_nCS ; (1 pterm, 2 signals) X_IMX_DAT_4_ = X_RAM_DAT_4_.PIN ; (1 pterm, 1 signal) X_IMX_DAT_4_.OE = !X_IMX_nOE & !X_IMX_nCS ; (1 pterm, 2 signals) X_IMX_DAT_5_ = X_RAM_DAT_5_.PIN ; (1 pterm, 1 signal) X_IMX_DAT_5_.OE = !X_IMX_nOE & !X_IMX_nCS ; (1 pterm, 2 signals) X_IMX_DAT_6_ = X_RAM_DAT_6_.PIN ; (1 pterm, 1 signal) X_IMX_DAT_6_.OE = !X_IMX_nOE & !X_IMX_nCS ; (1 pterm, 2 signals) X_IMX_DAT_7_ = X_RAM_DAT_7_.PIN ; (1 pterm, 1 signal) X_IMX_DAT_7_.OE = !X_IMX_nOE & !X_IMX_nCS ; (1 pterm, 2 signals) X_IMX_DAT_8_ = X_RAM_DAT_8_.PIN ; (1 pterm, 1 signal) X_IMX_DAT_8_.OE = !X_IMX_nOE & !X_IMX_nCS ; (1 pterm, 2 signals) X_IMX_DAT_9_ = X_RAM_DAT_9_.PIN ; (1 pterm, 1 signal) X_IMX_DAT_9_.OE = !X_IMX_nOE & !X_IMX_nCS ; (1 pterm, 2 signals) X_PLD_LED = 1 ; (1 pterm, 0 signal) X_RAM_ADR_0_ = X_IMX_ADR_0_ ; (1 pterm, 1 signal) X_RAM_ADR_10_ = X_IMX_ADR_10_ ; (1 pterm, 1 signal) X_RAM_ADR_11_ = X_IMX_ADR_11_ ; (1 pterm, 1 signal) X_RAM_ADR_12_ = X_IMX_ADR_12_ ; (1 pterm, 1 signal) X_RAM_ADR_13_ = X_IMX_ADR_13_ ; (1 pterm, 1 signal) X_RAM_ADR_14_ = X_IMX_ADR_14_ ; (1 pterm, 1 signal) X_RAM_ADR_15_ = X_IMX_ADR_15_ ; (1 pterm, 1 signal) X_RAM_ADR_16_ = 0 ; (0 pterm, 0 signal) X_RAM_ADR_17_ = 0 ; (0 pterm, 0 signal) X_RAM_ADR_1_ = X_IMX_ADR_1_ ; (1 pterm, 1 signal) X_RAM_ADR_2_ = X_IMX_ADR_2_ ; (1 pterm, 1 signal) X_RAM_ADR_3_ = X_IMX_ADR_3_ ; (1 pterm, 1 signal) X_RAM_ADR_4_ = X_IMX_ADR_4_ ; (1 pterm, 1 signal) X_RAM_ADR_5_ = X_IMX_ADR_5_ ; (1 pterm, 1 signal) X_RAM_ADR_6_ = X_IMX_ADR_6_ ; (1 pterm, 1 signal) X_RAM_ADR_7_ = X_IMX_ADR_7_ ; (1 pterm, 1 signal) X_RAM_ADR_8_ = X_IMX_ADR_8_ ; (1 pterm, 1 signal) X_RAM_ADR_9_ = X_IMX_ADR_9_ ; (1 pterm, 1 signal) X_RAM_DAT_0_ = X_IMX_DAT_0_.PIN ; (1 pterm, 1 signal) X_RAM_DAT_0_.OE = !X_IMX_nWE & !X_IMX_nCS ; (1 pterm, 2 signals) X_RAM_DAT_10_ = X_IMX_DAT_10_.PIN ; (1 pterm, 1 signal) X_RAM_DAT_10_.OE = !X_IMX_nWE & !X_IMX_nCS ; (1 pterm, 2 signals) X_RAM_DAT_11_ = X_IMX_DAT_11_.PIN ; (1 pterm, 1 signal) X_RAM_DAT_11_.OE = !X_IMX_nWE & !X_IMX_nCS ; (1 pterm, 2 signals) X_RAM_DAT_12_ = X_IMX_DAT_12_.PIN ; (1 pterm, 1 signal) X_RAM_DAT_12_.OE = !X_IMX_nWE & !X_IMX_nCS ; (1 pterm, 2 signals) X_RAM_DAT_13_ = X_IMX_DAT_13_.PIN ; (1 pterm, 1 signal) X_RAM_DAT_13_.OE = !X_IMX_nWE & !X_IMX_nCS ; (1 pterm, 2 signals) X_RAM_DAT_14_ = X_IMX_DAT_14_.PIN ; (1 pterm, 1 signal) X_RAM_DAT_14_.OE = !X_IMX_nWE & !X_IMX_nCS ; (1 pterm, 2 signals) X_RAM_DAT_15_ = X_IMX_DAT_15_.PIN ; (1 pterm, 1 signal) X_RAM_DAT_15_.OE = !X_IMX_nWE & !X_IMX_nCS ; (1 pterm, 2 signals) X_RAM_DAT_1_ = X_IMX_DAT_1_.PIN ; (1 pterm, 1 signal) X_RAM_DAT_1_.OE = !X_IMX_nWE & !X_IMX_nCS ; (1 pterm, 2 signals) X_RAM_DAT_2_ = X_IMX_DAT_2_.PIN ; (1 pterm, 1 signal) X_RAM_DAT_2_.OE = !X_IMX_nWE & !X_IMX_nCS ; (1 pterm, 2 signals) X_RAM_DAT_3_ = X_IMX_DAT_3_.PIN ; (1 pterm, 1 signal) X_RAM_DAT_3_.OE = !X_IMX_nWE & !X_IMX_nCS ; (1 pterm, 2 signals) X_RAM_DAT_4_ = X_IMX_DAT_4_.PIN ; (1 pterm, 1 signal) X_RAM_DAT_4_.OE = !X_IMX_nWE & !X_IMX_nCS ; (1 pterm, 2 signals) X_RAM_DAT_5_ = X_IMX_DAT_5_.PIN ; (1 pterm, 1 signal) X_RAM_DAT_5_.OE = !X_IMX_nWE & !X_IMX_nCS ; (1 pterm, 2 signals) X_RAM_DAT_6_ = X_IMX_DAT_6_.PIN ; (1 pterm, 1 signal) X_RAM_DAT_6_.OE = !X_IMX_nWE & !X_IMX_nCS ; (1 pterm, 2 signals) X_RAM_DAT_7_ = X_IMX_DAT_7_.PIN ; (1 pterm, 1 signal) X_RAM_DAT_7_.OE = !X_IMX_nWE & !X_IMX_nCS ; (1 pterm, 2 signals) X_RAM_DAT_8_ = X_IMX_DAT_8_.PIN ; (1 pterm, 1 signal) X_RAM_DAT_8_.OE = !X_IMX_nWE & !X_IMX_nCS ; (1 pterm, 2 signals) X_RAM_DAT_9_ = X_IMX_DAT_9_.PIN ; (1 pterm, 1 signal) X_RAM_DAT_9_.OE = !X_IMX_nWE & !X_IMX_nCS ; (1 pterm, 2 signals) X_RAM_nCS = X_IMX_nCS ; (1 pterm, 1 signal) X_RAM_nLB = 0 ; (0 pterm, 0 signal) X_RAM_nOE = X_IMX_nOE ; (1 pterm, 1 signal) X_RAM_nUB = 0 ; (0 pterm, 0 signal) X_RAM_nWE = X_IMX_nWE ; (1 pterm, 1 signal)