View source for DHCOM STM32MP1 Linux

== Linux virtual machine for development ==
:* Please have a look at: '''[[Virtual Machine for Application Development]]'''

== Linux Kernel ==

<!-- === Sources: Look at page [[DHCOM iMX6ULL-D2#BSP Sources|i.MX6ULL BSP Sources]] === -->

=== How to build a Kernel ===
{| class="wikitable" align="center" |  style="width: 98%; background: #f3f3f3;" valign="top" |
|
Get sources from Github
{| class="wikitable" style="width: 100%; color: #000000; background: #ffffff;" |
|
1. Start the Console on Linux<br/>
2. <tt>''git clone https://github.com/dh-electronics/linux-stm32mp1.git --branch dev/5.4.69_dhsom''</tt><br/>
3. <tt>''cd linux-stm32mp1''</tt>
|}
Configure and build the Device Tree + Kernel
{| class="wikitable" style="width: 100%; color: #000000; background: #ffffff;" |
| 
4. <tt>''ARCH=arm CROSS_COMPILE=/opt/gcc-arm-8.3-2019.03-x86_64-arm-linux-gnueabihf/bin/arm-linux-gnueabihf- make stm32mp1_dhsom_defconfig''</tt><br/>
5. <tt>''ARCH=arm CROSS_COMPILE=/opt/gcc-arm-8.3-2019.03-x86_64-arm-linux-gnueabihf/bin/arm-linux-gnueabihf- make menuconfig''</tt> (optional: If you want to add/remove Kernel features)<br/>
6. <tt>''ARCH=arm CROSS_COMPILE=/opt/gcc-arm-8.3-2019.03-x86_64-arm-linux-gnueabihf/bin/arm-linux-gnueabihf- make dtbs''</tt><br/>
7. <tt>''ARCH=arm CROSS_COMPILE=/opt/gcc-arm-8.3-2019.03-x86_64-arm-linux-gnueabihf/bin/arm-linux-gnueabihf- make zImage</tt>
|}
Create the FIT-image with our script ([https://www.dropbox.com/s/0jtyget66cxgq30/dh-create-fitimage_1.0_all.deb?raw=1 Download link])
{| class="wikitable" style="width: 100%; color: #000000; background: #ffffff;" |
|-
| '''Interactive mode for selecting device trees'''
| '''Device trees are set as parameter'''
|-
|
8. <tt>''create_fitimage''</tt><br/>
Enter the numbers (space seperated) of the device trees to include (e.g. if you want to include the device tree for the PDK2 include the number of <tt>''./arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dtb''</tt> (usually 3).<br/>
Enter the numbers (space seperated) of the device trees overlays to include (e.g. for the PDK2 enter the files which contain <tt>''PDK2''</tt> (usually 8 9 10 11 12 13 14).
|
(Example is for the PDK2) <br>
8. <tt>''create_fitimage --dtb ./arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dtb --dtbo ./arch/arm/boot/dts/stm32mp157c-dhcom-pdk2-overlay-460-200-x11.dtbo,./arch/arm/boot/dts/stm32mp157c-dhcom-pdk2-overlay-497-200-x12.dtbo,./arch/arm/boot/dts/stm32mp157c-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh.dtbo,./arch/arm/boot/dts/stm32mp157c-dhcom-pdk2-overlay-531-100-x21.dtbo,./arch/arm/boot/dts/stm32mp157c-dhcom-pdk2-overlay-531-100-x22.dtbo,./arch/arm/boot/dts/stm32mp157c-dhcom-pdk2-overlay-560-200-x12.dtbo,./arch/arm/boot/dts/stm32mp157c-dhcom-pdk2-overlay-638-100-x12-rpi7inch.dtbo''</tt>
|}
|}

== Kernel Userspace Interfaces to Access Hardware == 

=== Control GPIOs ===
:Show gpio definition in Linux
:{| class="wikitable"
|<tt>''gpioinfo''</tt>
|}
:: '''Note:'''
:: gpiochip0 = STM port-A, gpiochip1 = STM port-B, ...

:{|class="wikitable" style="text-align: center; width: 800px"
|-
! DHCOM Name: !! alt. DHCOM Name: !! SO-DIMM Pin# !! CPU Pad Name !! gpiod label:
|-
| GPIO A || || 154 || PF3 || DHCOM-A
|-
| GPIO B || || 156 || PD6 || DHCOM-B
|-
| GPIO C || || 162 || PG0 || DHCOM-C
|-
| GPIO D || || 163 || PD12 || DHCOM-D
|-
| GPIO E || || 164 || PC6 || DHCOM-E
|-
| GPIO F || || 165 || PD11 || DHCOM-F
|-
| GPIO G || || 167 || PI0 || DHCOM-G
|-
| GPIO H || || 173 || PI2 || DHCOM-H
|-
| GPIO I || || 175 || PI3 || DHCOM-I
|-
| GPIO J || CIF HSYNC || 74 || PH8 || DHCOM-J
|-
| GPIO K || CIF PCLK || 72 || PA6 || DHCOM-K
|-
| GPIO L || CIF MCLK || 70 || PG8 || DHCOM-L
|-
| GPIO M || CIF VSYNC || 68 || PI5 || DHCOM-M
|-
| GPIO N || CIF D9 || 66 || PH7 || DHCOM-N
|-
| GPIO O || CIF D8 || 64 || PI1 || DHCOM-O
|-
| GPIO P || CIF D7 || 62 || PE6 || DHCOM-P
|-
| GPIO Q || CIF D6 || 60 || PB8 || DHCOM-Q
|-
| GPIO R || CIF D5 || 58 || PI4 || DHCOM-R
|-
| GPIO S || CIF D4 || 56 || PH14 || DHCOM-S
|-
| GPIO T || CIF D3 || 54 || PH12 || DHCOM-T
|-
| GPIO U || CIF D2 || 52 || PH11 || DHCOM-U
|-
| GPIO V || CIF D1 || 50 || PH10 || DHCOM-V
|-
| GPIO W || CIF D0 || 48 || PH9 || DHCOM-W
|-
| INT HIGHEST PRIORITY || || 151 || PI8 || DHCOM-INT
|}

::'''Set state'''
::{| class="wikitable"
|<tt>''gpioset $(gpiofind DHCOM-<#>)=0''</tt>
|-
|<tt>''gpioset $(gpiofind DHCOM-<#>)=1''</tt>
|}

::or
::{| class="wikitable"
|<tt>''gpioset gpiochip<port#> <pin#>=0''</tt>
|-
|<tt>''gpioset gpiochip<port#> <pin#>=1''</tt>
|}

::'''Get state'''
::{| class="wikitable"
|<tt>''gpioget $(gpiofind DHCOM-<#>)''</tt>
|}

::or
::{| class="wikitable"
|<tt>''gpioget gpiochip<port#> <pin#>''</tt>
|}

=== RS-485 (only picoITX or DRC02) ===
:'''RS-485 device'''
:{| class="wikitable" style="width: 400px"
 ||DHCOM UART 2||<tt>/dev/ttySTM2</tt>
 |}

:'''Compilation on target'''
:{| class="wikitable"
|<tt>''gcc tty_rs485_test_v1.1.c -o tty_rs485_test''</tt>
|-
|<tt>''gcc tty_rs485_flags_v1.0.c -o tty_rs485_flags''</tt>
|}

:'''Show UART flags'''
:{| class="wikitable"
|<tt>''./tty_rs485_flags /dev/ttySTM2''</tt>
|}

:'''Set tty device to raw mode'''
:{| class="wikitable"
|<tt>''stty -F /dev/ttySTM2 115200 raw -echo -echoe''</tt>
|}

:'''Send data with demo program'''
:{| class="wikitable"
|<tt>''echo -n -e "\n\rHallo RS485 Welt!" &brvbar; ./tty_rs485_test /dev/ttySTM2''</tt>
|}

:'''Receive data with demo program'''
:{| class="wikitable"
|<tt>''./tty_rs485_test /dev/ttySTM2''</tt>
|}

:'''Download example source code'''
:* [[media:tty_rs485_test_v1.1.zip | tty_rs485_test_v1.1.c & tty_rs485_flags_v1.0.c]]

=== CAN interface ===
:'''Setup CAN interface with baudrate 500kbit/sec.'''
:{| class="wikitable"
|<tt>''ip link set can0 up type can bitrate 500000''</tt>
|}

:'''Start to listen on CAN port'''
:{| class="wikitable"
|<tt>''candump can0''</tt>
|}

:'''Send test message'''
:{| class="wikitable"
|<tt>''cansend can0 100#11.2233.44556677.88''</tt>
|}

:'''Deinitialize CAN port'''
:{| class="wikitable"
|<tt>''ip link set can0 down''</tt>
|}

=== UART Interfaces ===
:{| class="wikitable" style="width: 400px"
 ||DHCOM UART 1 ||<tt>/dev/ttySTM0</tt>
 |-
 ||DHCOM UART 2 ||<tt>/dev/ttySTM2</tt>
 |-
 ||DHCOM UART 3 ||<tt>/dev/ttySTM1</tt>
 |}

=== I2C Interfaces ===
:{| class="wikitable" style="width: 400px"
 ||DHCOM I2C 1||<tt>/dev/i2c-1</tt>
 |-
 ||DHCOM I2C 2 ||<tt>/dev/i2c-0</tt>
 |-
 ||On Module Devices ||<tt>/dev/i2c-2</tt>
 |}

=== ADC/DAC Interfaces ===
:{|class="wikitable" style="text-align: center; width: 800px"
|-
! DHCOM Name !! SO-DIMM Pin# !! PDK2 Header !! Linux device !! sysfs in/out name !! STM32MP1 pin
|-
| AD0 || 8 || X18 Pin 8|| iio:device2 || in_voltage0_* || ANA0
|-
| AD1 || 6 || X18 Pin 6 || iio:device3 || in_voltage1_* || ANA1
|-
| AD2 || 4 || X18 Pin 4 || iio:device0 || out_voltage1_* || PA4_DAC_OUT1
|-
| AD3 || 2 || X18 Pin 2 || iio:device1 || out_voltage2_* || PA5_DAC_OUT2
|}

==== ADC inputs ====
:sysfs path 
:{| class="wikitable"
|<tt>''/sys/bus/iio/devices/iio:device*''</tt>
|}

:Show offset and voltage scale
:{| class="wikitable"
|<tt>''cat in_voltage_scale''</tt>
|-
|<tt>''cat in_voltage_offset''</tt>
|}

: '''Notes:'''
:*Voltage = (RAW + OFFSET) * SCALE
:*Maximum input voltage = 2.9V (VDDA is connected to PMIC LDO1)

:Read analog value
:{| class="wikitable"
|<tt>''cat in_voltage*_raw''</tt>
|}

==== DAC outputs ====
:sysfs path 
:{| class="wikitable"
|<tt>''/sys/bus/iio/devices/iio:device*''</tt>
|}

:Show output voltage scale
:{| class="wikitable"
|<tt>''cat out_voltage*_scale''</tt>
|}

:Enable DAC
:{| class="wikitable"
|<tt>''echo 0 > out_voltage*_powerdown''</tt>
|}

: '''Notes:'''
:*Voltage = RAW * SCALE
:*Maximum output voltage = 2.9V (VDDA is connected to PMIC LDO1)

:Set analog output value
:{| class="wikitable"
|<tt>''echo xxxx > out_voltage*_raw''</tt>
|}

== FAQ ==
==== Connect to  WiFi network with WPA2 PSK ====

==== Set up WiFi AP ====
==== How to enable WiFi/BT support, if missing? How to configure RSI mode (WiFi alone, Bluetooth, ...)? ====
The needed sdmmc3 interface will be activated by the stm32mp15xx-dhcom-som.dtsi file. This is included by default with picoITX, PDK2 and DRC02 configuration.

Next to this the kernel module is needed. The Yocto build instructions can be found at the following file: 
https://github.com/dh-electronics/meta-dhsom-stm32-bsp/blob/dunfell-3.1/conf/machine/dh-stm32mp1-dhcom-picoitx.conf

 # Ship kernel modules
 MACHINE_ESSENTIAL_EXTRA_RDEPENDS += " linux-firmware-rs9116 "
 KERNEL_MODULE_AUTOLOAD += " rsi_sdio "
 KERNEL_MODULE_PROBECONF += " rsi_sdio "
 module_conf_rsi_sdio = "options rsi_sdio dev_oper_mode=1"

If you are using a different root filesystem (compared to our Yocto configuration) please ensure, that the firmware files and the rsi_sdio.conf file are included in the filesystem:
:[[media:rsi_firmware.zip|rsi_firmware.zip]]
:* Copy the directory rsi to /lib/firmware/
:* Copy the file rsi_sdio.conf to /etc/modprobe.d/

'''Note to DRC02:'''
DRC02 default images with date Oct. 2021 or newer support WiFi/BT by an additional device tree overlay. 

By default, the RSI module is configured to WiFi alone mode with our Yocto image. The mode can be configured by rsi_sdio.conf file:
 According to Linux kernel source, the dev_oper_mode has the following meaning:
 linux-2.6$ git grep -n DEV_OPMODE_ drivers/net/wireless/rsi/ [...]
 drivers/net/wireless/rsi/rsi_hal.h:21:#define DEV_OPMODE_WIFI_ALONE     1
 drivers/net/wireless/rsi/rsi_hal.h:22:#define DEV_OPMODE_BT_ALONE       4
 drivers/net/wireless/rsi/rsi_hal.h:23:#define DEV_OPMODE_BT_LE_ALONE    8
 drivers/net/wireless/rsi/rsi_hal.h:24:#define DEV_OPMODE_BT_DUAL        12
 drivers/net/wireless/rsi/rsi_hal.h:25:#define DEV_OPMODE_STA_BT         5
 drivers/net/wireless/rsi/rsi_hal.h:26:#define DEV_OPMODE_STA_BT_LE      9
 drivers/net/wireless/rsi/rsi_hal.h:27:#define DEV_OPMODE_STA_BT_DUAL    13
 drivers/net/wireless/rsi/rsi_hal.h:28:#define DEV_OPMODE_AP_BT          6
 drivers/net/wireless/rsi/rsi_hal.h:29:#define DEV_OPMODE_AP_BT_DUAL     14

If you like to use Bluetooth alone mode, change dev_oper_mode to 12. Then you can use the standard hci commands. Start with 'hciconfig hci0 up' to activate the interface.

==== USB 1.1 problems: Custom board without USB 2.0 hub inbetween the MP1 USB host port? ====
And in that case, have a look at arch/arm/boot/dts/stm32mp15xx-dhcom-picoitx.dtsi and how the OHCI (!) is enabled there. And of course, make sure the kernel config options are enabled accordingly (like for the PicoITX machine)

{| class="wikitable" | style="width: 100%; color: #000000; background: #FFFFFF;" valign="top" |
|
<tt>meta-dhsom-stm32-bsp$ git grep OHCI</tt>
|}

{| class="wikitable" | style="width: 100%; color: #000000; background: #FFFFFF;" valign="top" |
|
<tt>recipes-kernel/linux/linux-stable/5.10/dh-stm32mp1-common/dh-stm32mp1-dhsom-common.cfg:CONFIG_USB_OHCI_HCD=y</tt><br/>
<tt>recipes-kernel/linux/linux-stable/5.10/dh-stm32mp1-common/dh-stm32mp1-dhsom-common.cfg:CONFIG_USB_OHCI_HCD_PLATFORM=y</tt>
|}

arch/arm/boot/dts/stm32mp15xx-dhcom-picoitx.dtsi snippet:
 &usbh_ehci {
          phys = <&usbphyc_port0>;
          status = "okay";
 };
 
 &usbh_ohci { // <---------------- HERE
          phys = <&usbphyc_port0>;
          status = "okay";
 };
 
 &usbotg_hs {
          dr_mode = "otg";
          pinctrl-0 = <&usbotg_hs_pins_a>;
          pinctrl-names = "default";
          phy-names = "usb2-phy";
          phys = <&usbphyc_port1 0>;
          vbus-supply = <&vbus_otg>;
          status = "okay";
 };
 
 &usbphyc {
          status = "okay";
 };
 
 &usbphyc_port0 {
          phy-supply = <&vdd_usb>;
          vdda1v1-supply = <&reg11>;
          vdda1v8-supply = <&reg18>;
 };
 
 &usbphyc_port1 {
          phy-supply = <&vdd_usb>;
          vdda1v1-supply = <&reg11>;
          vdda1v8-supply = <&reg18>;
 };

==== System stability or USB Host problems? ====
If a display with higher resolution and pixel clock > 48 MHz is used, then this can case USB host and/or system stability problems.

Workaround:
The OSPEEDR must be set to OSPEEDR = 1 for LCD_CLK and OSPEEDR = 0 for all other LTDC signals.
 &pinctrl {
 	ltdc_pins_ customhmi: ltdc-dh-1 {
 		pins1 {
 			pinmux = <STM32_PINMUX('I', 14, AF14)>; /* LCD_CLK */
 			bias-disable;
 			drive-push-pull;
 			'''slew-rate = <1>;'''
 		};
 		pins2 {
 				pinmux = <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */
 				 <STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */
                                  ...
 				 <STM32_PINMUX('K',  6, AF14)>; /* LCD_B7 */
 			bias-disable;
 			drive-push-pull;
 			'''slew-rate = <0>;'''
 		};
 	};
 	
 	ltdc_sleep_pins_ customhmi: ltdc-sleep-dh-1 {
 		pins {
 			pinmux = <STM32_PINMUX('I', 14, ANALOG)>, /* LCD_CLK */
                                  ...
 				 <STM32_PINMUX('K',  6, ANALOG)>; /* LCD_B7 */
 		};
 	};	
 };

==== USB OTG: Custom board where the USB-OTG port is only used as host? ====

On the DHCOM standard, the second USB port of the STM32MP1 is usually an USB-OTG port. If you have a custom board where you want to use the USB-OTG port in host mode only, you should consider the following:

The USB-OTG controller on the STM32MP1, DWC2, does support host mode but is rather inefficient (in comparison to a dedicated USB host controller). The following block diagram shows, that it is possible on the STM32MP1 to alter the pinmuxing, so that the USB-OTG port is used with the USB Host controller of the STM32MP1 (instead of using the DWC2 OTG controller):   

    Host port#1: EHCI/OHCI controller _________ HS PHY port #1 (SoC balls D+/D- #1)
       
       
    Host port#2: EHCI/OHCI controller __ 
                                         \   
                                         |_____ HS PHY port #2 (SoC balls D+/D- #2)
    DWC2 OTG controller_________________/|
                                         |
            UTIM switch__________________|

This change can be made in the device tree with disabling the DWC2 controller and adding the second usb_phyc port to the nodes of usbh_ehci and (if applicable) usbh_ohci. These nodes are usually in the .dtsi file of the board (e.g. for the PicoITX: arch/arm/boot/dts/stm32mp15xx-dhcom-picoitx.dtsi). Here a is snippet how this could look like:

 &usbh_ehci {
          phys = <&usbphyc_port0>''', <&usbphyc_port1 1>'''; // <-------- HERE
          status = "okay";
 };
 
 &usbh_ohci { 
          phys = <&usbphyc_port0>''', <&usbphyc_port1 1>'''; // <-------- HERE
          status = "okay";
 };
 
 &usbotg_hs {
          '''status = "disabled";''' // <-------- HERE
 };
 
 &usbphyc {
          status = "okay";
 };
 
 &usbphyc_port0 {
          phy-supply = <&vdd_usb>;
          vdda1v1-supply = <&reg11>;
          vdda1v8-supply = <&reg18>;
 };
 
 &usbphyc_port1 {
          phy-supply = <&vdd_usb>;
          vdda1v1-supply = <&reg11>;
          vdda1v8-supply = <&reg18>;
 };

==== How to try QtWebengine ====
The QtWebengine is part of the DH default images. 
Please stop the Weston desktop, before the start of the Browser.
 Older images: "systemctl stop weston@root.service"  
 Newer images: "systemctl stop weston.service"
How to start the Browser:
 QT_QPA_PLATFORM=eglfs QT_QPA_EGLFS_ALWAYS_SET_MODE=1 QT_QPA_EGLFS_KMS_CONFIG=/etc/default/qt5-eglfs-kms.json qtwebengine-minimal http://YOUR-TEST-PAGE/ --no-sandbox

==== How is the Browser Perfomance on the STM32MP1? ====
[https://wiki.dh-electronics.com/index.php/STM32MP1_Browser_Performance STM32MP1 Browser Performance]