View source for DHCOM STM32MP1-D2

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== Hardware ==

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* '''Dual ARM Cortex®-A7 up to 650 MHz and Single ARM Cortex®-M4 up to 209 MHz'''
* 3D GPU OpenGL® ES2.0 up to 533 MHz, Power Management: STPMIC1A
* TrustZone, cryptography, hash, secure boot
* DDR3L: 256 / 512 / 1024 Mbyte (32 bit)
* eMMC flash: 4 / 8 / 16 GB
* 2 MByte SPI boot flash
* 256 byte EEPROM
* WiFi / Bluetooth: WiFi IEEE 802.11 a/b/g/n, 802.11j (hosted mode) with dual band, Bluetooth® v5.0 (BR/EDR/BLE), PCB antenna and U.FL antenna connector
* On-board microSD card socket 
* RTC with temperature compensation ± 3.0 ppm between -40 to +85°C
* Supply voltage range: 3.3 or 5.0 VDC / typ. 1 W-1.5 W (without WiFi/BT)
* Industrial temperature range (-40°C to +85°C)
* SODIMM-200 socket with DHCOM pin assignment
* JTAG debug connection via FFC plug connector or Tag-Connect
* Bus interface: 16 bit asynchron address/data bus, 1 CS
* Ethernet 1: 10 / 100 Mbit with PHY, IEEE 1588v2
* Ethernet 2: 10 / 100 Mbit with PHY
* MMC/SD interface:	4 bit mode
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* CAN 1: V2.0B and CAN FD V1.0, TTCAN (time triggered)
* CAN 2: V2.0B and CAN FD V1.0
* UART 1: Rx / Tx / Rts / Cts, up to 12.5 Mbit/s
* UART 2: Rx / Tx / Rts / Cts, up to 12.5 Mbit/s
* UART 3: Rx / Tx, up to 12.5 Mbit/s
* SPI 1: max. 50 Mbit/s
* I2C 1: max. 1 Mbit/s
* I2C 2: max. 1 Mbit/s
* USB host 1: High-Speed
* USB OTG: High-Speed
* Parallel camera: 10 bit interface up to 140 Mbytes/s
* Display RGB: Max. 1366 x 768 pixels, 24 bit
* MIPI®-DSI 2 data lanes up to 1 GHz each
* Touch: 4-wire
* I²S Audio interface
* GPIOs: 24 IOs
* PWM: 1x 16 bit
* Analog: 4x 16 bit ADC and 2x 12 bit DAC
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*[[DHCOM STM32MP1 Hardware|Hardware Support]]

== Product Change Notifications (PCN) ==
* [[media:PCN_DHCOM-STM32MP1-001_R01_2020-10-29.pdf|PCN_DHCOM-STM32MP1-001_R01_2020-10-29.pdf (high speed microSD switch EOL)]]
* [[media:PCN_DHCOM-STM32MP1-002_R01_2021-12-23.pdf|PCN_DHCOM-STM32MP1-002_R01_2021-12-23.pdf (microSD socket EOL)]]
* [[media:PCN_DHCOM-STM32MP15-003_R01_2023-05-22.pdf|PCN_DHCOM-STM32MP15-003_R01_2023-05-22.pdf (U-Boot Update)]]

== Software Support ==
*[[DHCOM STM32MP1 Bootloader U-Boot|STM32MP1: Bootloader U-Boot]]
*[[DHCOM STM32MP1 Linux|STM32MP1: Linux]]
*[[OpenOCD JTAG on STM32MP1|How to use JTAG on STM32MP1]]
*[[IPC|Inter‐Processor Communication (Cortex-A7 to Cortex-M4)]]
*[[Debugging_M4_on_STM32MP15xxxx|STM32MP1: Debugging M4]]
*[[Add Yocto SDK with QT5 to QT Creator | Start with Qt]]
*[[U-Boot recovery for STM32MP1 DHSOM via DFU |U-Boot recovery for STM32MP1 DHSOM via DFU]]
*[[DHCOM STM32MP15 Secure Boot | Secure Boot]]

== BSP Sources ==
==== [https://www.denx.de/wiki/U-Boot U-Boot] ====
* [https://github.com/dh-electronics/u-boot-stm32mp1/tree/v2022.07_testbench U-Boot (based on v2022.07)]

==== [https://www.kernel.org Linux Kernel and Yocto] ====
* Mainline
* [https://github.com/dh-electronics/meta-dhsom-stm32-bsp Yocto BSP meta layer --> Github]
* [https://github.com/dh-electronics/kas-dhsom Easy Yocto build via KAS --> Github]

== Download binaries/images ==
=== PDK2 ===
* [https://www.dropbox.com/s/eknl5gr69fvpuwj/dh-image-demo-dh-stm32mp1-dhcom-pdk2-20211021081919_2021-10-21.rootfs.wic.xz?dl=0 DH Yocto based Starter Image 2021-10-21 (based on 5.10 kernel)]
* [https://www.dropbox.com/s/ll1z50cllwtw0j9/HD00066_Debian-Buster-PDK2_2021-11-03.img.gz?dl=0 DH Debian Starter Image 2021-11-03 (based on 5.10 kernel)]
=== DRC02 ===
* [https://www.dropbox.com/s/fv4yheno2v1pnqu/dh-image-demo-dh-stm32mp1-dhcom-drc02-20211021085758_2021-10-11.rootfs.wic.xz?dl=0 DH Yocto based Starter Image 2021-10-11 (based on 5.10 kernel)]
* [https://www.dropbox.com/s/e9r5amtjduga4a3/HD00066_Debian-Buster-DRC02_2021-11-02.img.gz?dl=0 DH Debian Starter Image 2021-11-02 (based on 5.10 kernel)]
=== picoITX ===
* [https://www.dropbox.com/s/gwhjv9oi1lt34s5/dh-image-demo-dh-stm32mp1-dhcom-picoitx_2021-10-21.wic.xz?dl=0 DH Yocto based Starter Image 2021-10-21 (based on 5.10 kernel)]
* [https://www.dropbox.com/s/9a3hc1crophlds6/DH00066_Debian-Buster-picoITX_2022-01-03.img.gz?dl=0 DH Debian Starter Image 2022-01-03 (based on 5.10 kernel)]