DHCOM iMX6ULL-D2: Difference between revisions

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== Product Change Notifications (PCN) ==
== Product Change Notifications (PCN) ==
:* [[media:PCN_DHCOR-iMX6ULL-001_R01_2020-02-18.pdf|PCN_DHCOR-iMX6ULL-001_R01_2020-02-18.pdf (IMX_THERMAL)]]
* [[media:PCN_DHCOR-iMX6ULL-001_R01_2020-02-18.pdf|PCN_DHCOR-iMX6ULL-001_R01_2020-02-18.pdf (IMX_THERMAL)]]
:* [[media:PCN_DHCOR-iMX6ULL-002_R01_2020-02-18.pdf|PCN_DHCOR-iMX6ULL-002_R01_2020-02-18.pdf (SPEED_GRADING)]]
* [[media:PCN_DHCOR-iMX6ULL-002_R01_2020-02-18.pdf|PCN_DHCOR-iMX6ULL-002_R01_2020-02-18.pdf (SPEED_GRADING)]]
:* [[media:PCN_DHCOR-iMX6ULL-003_R01_2020-02-18.pdf|PCN_DHCOR-iMX6ULL-003_R01_2020-02-18.pdf (Bootloader on eMMC)]]
* [[media:PCN_DHCOR-iMX6ULL-003_R01_2020-02-18.pdf|PCN_DHCOR-iMX6ULL-003_R01_2020-02-18.pdf (Bootloader on eMMC)]]
:* [[media:PCN_DHCOR-iMX6ULL-004_R01_2020-09-17.pdf|PCN_DHCOR-iMX6ULL-004_R01_2020-09-17.pdf (900MHz undervolt)]]
* [[media:PCN_DHCOR-iMX6ULL-004_R01_2020-09-17.pdf|PCN_DHCOR-iMX6ULL-004_R01_2020-09-17.pdf (900MHz undervolt)]]
:* [[media:PCN_DHCOR-iMX6ULL-005_R01_2021-05-05.pdf|PCN_DHCOR-iMX6ULL-005_R01_2021-05-05.pdf (VDD_SOC_CAP capacitor)]]
* [[media:PCN_DHCOR-iMX6ULL-005_R01_2021-05-05.pdf|PCN_DHCOR-iMX6ULL-005_R01_2021-05-05.pdf (VDD_SOC_CAP capacitor)]]
:* [[media:PCN_DHCOR-iMX6ULL-006_R02_2021-05-10.pdf|PCN_DHCOR-iMX6ULL-006_R02_2021-05-10.pdf (PMIC buck converter mode)]]
* [[media:PCN_DHCOR-iMX6ULL-006_R02_2021-05-10.pdf|PCN_DHCOR-iMX6ULL-006_R02_2021-05-10.pdf (PMIC buck converter mode)]]


== Software Support ==
== Software Support ==

Revision as of 13:01, 18 June 2021

DHCOR i.MX6ULL-LG
DHCOM iMX6ULL-D2

Scope

This is also the right page for the DHCOR module, because DHCOM is the reference design for the DHCOR module.

Hardware

  • Cortex-A7 NXP i.MX6ULL up to 900 MHz
  • 128 - 1024 MByte NAND flash memory (8 bit bus width) or
    4 - 16 GByte eMMC flash (8 bit bus width)
  • 2 MB SPI boot flash
  • 128 - 1024 MByte DDR3-400
  • On module microSD card socket (4 bit SDIO) [1]
  • LC display controller, 18 bit colors, 1366x768 pixels
  • On-chip touch controller for 4-wire resistive touch screens
  • 2x Ethernet controller 10/100 Mbit, IEEE1588 conform [2]
  • USB 2.0 OTG high-speed
  • USB 2.0 host high speed
  • 2x Standard UART with hardware handshake support [3][4]
  • WiFi iEEE802.11b/g/n + Bluetooth v4.1 (BR/EDR/BLE) module on BGA [1][4]


[1] On module microSD card socket is only available if WiFi is not mounted.
[2] The second SPI is only available, if the second ethernet is not mounted.
[3] CTS and RTS of the first UART is only available if second CAN port is not connected.
[4] The second UART is only available if Bluetooth is not used. This means WiFi/BT module 1DX is not mounted or module 1FX (only WiFi) is mounted.
[5] I²S lines are shared with JTAG.

  • 2x CAN interface [3]
  • 2x SPI interface [2]
  • 2x I²C interface
  • I²S Audio codec (1 x microphone, 1 x Line in, 1x Line out) [5]
  • Real-time clock (I²C connection), low power temperature compensated
  • 2x 10 bit analog input (I²C connection)
  • 2x 256 Bytes EEPROM with integrated MAC address
  • PWM channel
  • 22 GPIOs (A-U + INT_HI_PRIO)
  • JTAG debug connection via FFC plug connector
  • Industrial temperature range (-40°C to +85°C)
  • SODIMM-200 socket with DHCOM pin assignment

Product Change Notifications (PCN)

Software Support

BSP Sources

U-Boot

Linux Kernel

  • Mainline

Download binaries/images

U-Boot (for eMMC DHCOMs)

More on how to program it with the U-Boot command "update bootloader ..." on the page "DHCOM Update Mechanism"

Update Kernel

More on how to use it on the page "DHCOM Update Mechanism"

Debian based images

  • Debian 10 "Buster" + Kernel 4.19.135 Release 2020-12-01
Open it with Disks by double click on Debian Linux. Use balenaEtcher on Windows.
Extract the files on a USB stick (MBR / FAT32) and insert it into your board / device. More about the files on the page "DHCOM Update Mechanism"

Hint: You can also progam the eMMC by using the U-Boot command "ums" (usable since U-Boot v2018.05)