DHCOM iMX6-D2: Difference between revisions

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* [https://www.dropbox.com/s/jw823q3ot4iim06/u-boot-with-spl_imx6_v2.0.8.0_emmc.imx?raw=1 DH U-Boot v2.0.8.0 (based on v2018.05)]
* [https://www.dropbox.com/s/jw823q3ot4iim06/u-boot-with-spl_imx6_v2.0.8.0_emmc.imx?raw=1 DH U-Boot v2.0.8.0 (based on v2018.05)]
* [https://www.dropbox.com/s/qagp43dfd6mjklm/v1-1-0-7_u-boot-imx6qdl.tar.xz?raw=1 DH U-Boot v1.1.0.7 (based on v2015.10)]
* [https://www.dropbox.com/s/qagp43dfd6mjklm/v1-1-0-7_u-boot-imx6qdl.tar.xz?raw=1 DH U-Boot v1.1.0.7 (based on v2015.10)]
: [[DHCOM Update Mechanism#Commandline Mode|Hint: Program it with U-Boot command "update bootloader ..."]]
: [[DHCOM Update Mechanism#Commandline Mode|More on how to program it on page "DHCOM Update Mechanism"]]


==== Update Kernel ====
==== Update Kernel ====
* [https://www.dropbox.com/s/x46x2u2081fwln3/2018-02-01_imx6_updatekernel.zip?raw=1 Update Kernel Release 2018-02-01]
* [https://www.dropbox.com/s/x46x2u2081fwln3/2018-02-01_imx6_updatekernel.zip?raw=1 Update Kernel Release 2018-02-01]
: [[DHCOM Update Mechanism|More on how to use it on page "DHCOM Update Mechanism"]]


==== Debian based images ====
==== Debian based images ====

Revision as of 12:08, 3 March 2020

COM iMX6-D2

Hardware

  • Cortex-A9 Freescale i.MX6 Solo/DualLite/Dual/Quad up to 1.2GHz
  • 2D (GC320) / 3D (GC880/GC2000) graphics accelerator
  • 128 - 1024 MByte NAND flash memory (8 bit bus width) or
    4 - 16 GByte eMMC flash (8 bit bus width)
  • 2 MB SPI boot flash
  • 256 - 2048 MByte DDR3-1066 or DDR3-800
  • On module microSD card socket (4 bit SDIO) [1]
  • SD/MMC card interface, 4 bit SDIO
  • LC display controller, 24 bit colors, 2048x1536 pixels
  • LVDS 4-channel, max. 165 Mpixels/s
  • On-board touch controller for 4-wire resistive touch screens
  • Ethernet controller 10/100 Mbit, IEEE1588 conform
  • USB 2.0 OTG high-speed
  • USB 2.0 host high speed
  • Full function UART [2]
  • Standard UART with hardware handshake support
  • Standard UART


[1] On module microSD card socket is only available if second CAN port is not connected.
[2] CTS and RTS is only available if second CAN port is not connected.

  • 2x CAN interface [1][2]
  • 2x SPI interface
  • 2x I²C interface
  • I²S Audio codec (1 x microphone, 1 x Line in, 1x Line out)
  • Real-time clock (I²C connection), low power temperature compensated
  • 12 bit analog input
  • 128 Bytes EEPROM with integrated MAC address
  • 16 bit address/databus interface on SODIMM-200 socket
  • PWM channel
  • 24 GPIOs (A-W + INT_HI_PRIO)
  • JTAG debug connection via FFC plug connector
  • Industrial temperature range (-40°C to +85°C)
  • SODIMM-200 socket with DHCOM pin assignment

Software Support

BSP Sources

U-Boot

Linux Kernel

  • Mainline
  • NXP Vendor

Download binaries/images

U-Boot (for eMMC COMs)

More on how to program it on page "DHCOM Update Mechanism"

Update Kernel

More on how to use it on page "DHCOM Update Mechanism"

Debian based images

  • Debian 8 "Jessie" + Kernel 4.4.60 Release 2017-05-29
  • Debian 8 "Jessie" with Qt5.9.1 + Vendor Kernel 4.1.15 Release 2017-10-06

Download Linux code examples

Code Examples for Userspace-Applications to Access SPI, I2C, GPIOs, and more

Download WEC

WEC7 DHHalLib.dll (function library)

WEC7 binary BSP

WEC2013 DHHalLib.dll (function library)

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