DHCOM STM32MP1 Linux: Difference between revisions

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=== DHSOM device tree structure ===
DHCOM and PDK2
--------------
* stm32mp15xx-dhcom-som.dtsi [1] -------------------------.
    [ STM32MP15xx based DHCOM SoM DT, common for all    ]  |
    [ variants of the SoC populated on the SoM.        ]  +--.
                                                            |  |
* stm32mp15xx-dhcom-pdk2.dtsi -----------------------------'  |
    [ STM32MP15xx based DHCOM PDK2 carrier board DT,    ]      |
    [ common for all of the PDK2 and SoM combinations.  ]      |
                                                              |
    * stm32mp157c-dhcom-pdk2.dts <-----------------------------'
      [ STM32MP157C based DHCOM SoM populated on PDK2  ]      :
      [ carrier board combined DT. This DT describes    ]      :
      [ specific combination of SoM populated on PDK2  ]      :
      [ carrier board.                                  ]      :
                                                              :
                                                              :
        Both common SoM and PDK2 DTs can be extended by DTOs  :
    .- - - - - - - - - - - - - - - - - - - - - - - - - - - - - '
    :  DTOs add additional bindings into base DTs at runtime.
    :
    :
    * stm32mp15xx-dhcom-pdk2-overlay-460-200-x11.dts
    : [ DH 460-200 FMC2 SRAM expansion card inserted into header X11.  ]
    :
    * stm32mp15xx-dhcom-pdk2-overlay-497-200-x12.dts
    : [ DH 497-200 7" 800x480 DPI TFT LCD and resistive touchscreen    ]
    : [ expansion card inserted into header X12.                        ]
    : [ This DT uses common DPI panel base DT, see [2].                ]
    :
    * stm32mp15xx-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh.dts
    : [ DH 505-200 10" 1280x800 LVDS TFT LCD and capacitive            ]
    : [ touchscreen expansion card inserted into header X12.            ]
    : [ The panel interface is LVDS, connected to SoC via DPI-to-LVDS  ]
    : [ bridge chip OnSemi FIN3385.                                    ]
    : [ This DT uses common CH101 panel base DT, see [3].              ]
    :
    * stm32mp15xx-dhcom-pdk2-overlay-560-200-x12.dts
    : [ DH 560-200 7" 800x480 DPI TFT LCD and capacitive touchscreen    ]
    : [expansion card inserted into header X12.                        ]
    : [ This DT uses common DPI panel base DT, see [2].                ]
    :
    * stm32mp15xx-dhcom-pdk2-overlay-638-100-x12-rpi7inch.dts
    : [ DH 638-100 adapter card connected to 7" 800x480 DSI TFT LCD and ]
    : [ capacitive touchscreen module, and inserted into header X12.    ]
    : [ The panel interface is DPI, connected to SoC via DSI-to-DPI    ]
    : [ bridge chip Toshiba TC358762.                                  ]
    : [ This DT uses common DPI panel base DT, see [2].                ]
    :
    * stm32mp15xx-dhcom-pdk2-overlay-672-100-x18.dts
    : [ DH 672-100 CAN transceiver chip expansion board inserted into  ]
    : [ header X18.                                                    ]
    :
    * stm32mp15xx-dhcom-pdk2-overlay-531-100-x21.dts
    : [ DH 531-100 I2C and SPI EEPROM expansion board inserted into    ]
    : [ header X21.                                                    ]
    :
    * stm32mp15xx-dhcom-pdk2-overlay-531-100-x22.dts
      [ DH 531-100 I2C and SPI EEPROM expansion board inserted into    ]
      [ header X22.                                                    ]
DHCOM and PicoITX
-----------------
* stm32mp15xx-dhcom-som.dtsi -----------------------------.
    [ STM32MP15xx based DHCOM SoM DT, see also [1] above.]  |
                                                            +----.
                                                            |    |
* stm32mp15xx-dhcom-picoitx.dtsi --------------------------'    |
    [ STM32MP15xx based DHCOM PicoITX carrier board DT,  ]      |
    [ common for all of the PicoITX and SoM combinations.]      |
                                                                |
    * stm32mp157c-dhcom-picoitx.dts <----------------------------'
      [ STM32MP157C based DHCOM SoM populated on PicoITX ]      :
      [ carrier board combined DT. This DT describes    ]      :
      [ specific combination of SoM populated on PicoITX ]      :
      [ carrier board.                                  ]      :
                                                                :
                                                                :
        Both common SoM and PicoITX DTs can be extended by DTOs  :
    .- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - '
    :  DTOs add additional bindings into base DTs at runtime.
    :
    :
    * stm32mp15xx-dhcom-picoitx-overlay-548-200-x2-mi0700s4t-6.dts
    : [ DH 548-200 7" 800x480 DPI TFT LCD and resistive touchscreen  ]
    : [ expansion card inserted into header X2.                      ]
    :
    * stm32mp15xx-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh.dts
      [ DH 626-100 10" 1280x800 LVDS TFT LCD and capacitive          ]
      [ touchscreen expansion card inserted into header X2.          ]
      [ The panel interface is LVDS, connected to SoC via DPI-to-LVDS ]
      [ bridge chip OnSemi FIN3385.                                  ]
      [ This DT uses common CH101 panel base DT, see [3].            ]
DHCOM and DRC02
---------------
* stm32mp15xx-dhcom-som.dtsi -----------------------------.
    [ STM32MP15xx based DHCOM SoM DT, see also [1] above.]  |
                                                            +--.
                                                            |  |
* stm32mp15xx-dhcom-picoitx.dtsi --------------------------'  |
    [ STM32MP15xx based DHCOM DRC02 carrier board DT,  ]      |
    [ common for all of the DRC02 and SoM combinations.]      |
                                                              |
    * stm32mp153c-dhcom-picoitx.dts <--------------------------'
      [ STM32MP153C based DHCOM SoM populated on DRC02 ]      :
      [ carrier board combined DT. This DT describes  ]      :
      [ specific combination of SoM populated on DRC02 ]      :
      [ carrier board.                                ]      :
                                                              :
                                                              :
        Both common SoM and DRC02 DTs can be extended by DTOs  :
    .- - - - - - - - - - - - - - - - - - - - - - - - - - - - - '
    :  DTOs add additional bindings into base DTs at runtime.
    :
    :
    * stm32mp15xx-dhcom-drc02-overlay-wifi-rsi.dts
      [ DH DHCOM DRC02 populated with DHCOM carrying RSI WiFi.        ]
      [ The carrier board MicroSD card is not available in this setup.]
DHCOM common DTSIs
------------------
    * stm32mp15xx-dhcom-overlay-panel-dpi-ch101olhlwh.dtsi [3]
      [ Common CH101 panel DT bindings used by all DHCOM systems.    ]
      [ This DT uses common DPI panel base DT, see [2].              ]
    * stm32mp15xx-dhcom-overlay-panel-dpi.dtsi [2]
      [ Common DPI panel DT bindings used by all DHCOM systems.      ]


== Kernel Userspace Interfaces to Access Hardware ==  
== Kernel Userspace Interfaces to Access Hardware ==  


=== RS-485 on picoITX ===
=== Control GPIOs ===
:Show gpio definition in Linux
:{| class="wikitable"
|<tt>''gpioinfo''</tt>
|}
:: '''Note:'''
:: gpiochip0 = STM port-A, gpiochip1 = STM port-B, ...
 
:{|class="wikitable" style="text-align: center; width: 800px"
|-
! DHCOM Name: !! alt. DHCOM Name: !! SO-DIMM Pin# !! CPU Pad Name !! gpiod label:
|-
| GPIO A || || 154 || PF3 || DHCOM-A
|-
| GPIO B || || 156 || PD6 || DHCOM-B
|-
| GPIO C || || 162 || PG0 || DHCOM-C
|-
| GPIO D || || 163 || PD12 || DHCOM-D
|-
| GPIO E || || 164 || PC6 || DHCOM-E
|-
| GPIO F || || 165 || PD11 || DHCOM-F
|-
| GPIO G || || 167 || PI0 || DHCOM-G
|-
| GPIO H || || 173 || PI2 || DHCOM-H
|-
| GPIO I || || 175 || PI3 || DHCOM-I
|-
| GPIO J || CIF HSYNC || 74 || PH8 || DHCOM-J
|-
| GPIO K || CIF PCLK || 72 || PA6 || DHCOM-K
|-
| GPIO L || CIF MCLK || 70 || PG8 || DHCOM-L
|-
| GPIO M || CIF VSYNC || 68 || PI5 || DHCOM-M
|-
| GPIO N || CIF D9 || 66 || PH7 || DHCOM-N
|-
| GPIO O || CIF D8 || 64 || PI1 || DHCOM-O
|-
| GPIO P || CIF D7 || 62 || PE6 || DHCOM-P
|-
| GPIO Q || CIF D6 || 60 || PB8 || DHCOM-Q
|-
| GPIO R || CIF D5 || 58 || PI4 || DHCOM-R
|-
| GPIO S || CIF D4 || 56 || PH14 || DHCOM-S
|-
| GPIO T || CIF D3 || 54 || PH12 || DHCOM-T
|-
| GPIO U || CIF D2 || 52 || PH11 || DHCOM-U
|-
| GPIO V || CIF D1 || 50 || PH10 || DHCOM-V
|-
| GPIO W || CIF D0 || 48 || PH9 || DHCOM-W
|-
| INT HIGHEST PRIORITY || || 151 || PI8 || DHCOM-INT
|}
 
::'''Set state'''
::{| class="wikitable"
|<tt>''gpioset $(gpiofind DHCOM-<#>)=0''</tt>
|-
|<tt>''gpioset $(gpiofind DHCOM-<#>)=1''</tt>
|}
 
::or
::{| class="wikitable"
|<tt>''gpioset gpiochip<port#> <pin#>=0''</tt>
|-
|<tt>''gpioset gpiochip<port#> <pin#>=1''</tt>
|}
 
::'''Get state'''
::{| class="wikitable"
|<tt>''gpioget $(gpiofind DHCOM-<#>)''</tt>
|}
 
::or
::{| class="wikitable"
|<tt>''gpioget gpiochip<port#> <pin#>''</tt>
|}
 
=== RS-485 (only picoITX or DRC02) ===
:'''RS-485 device'''
:'''RS-485 device'''
:{| class="wikitable" style="width: 400px"
:{| class="wikitable" style="width: 400px"
Line 50: Line 264:
:'''Compilation on target'''
:'''Compilation on target'''
:{| class="wikitable"
:{| class="wikitable"
|<tt>''gcc tty_rs485_test.c -o tty_rs485_test''</tt>
|<tt>''gcc tty_rs485_test_v1.1.c -o tty_rs485_test''</tt>
|-
|<tt>''gcc tty_rs485_flags_v1.0.c -o tty_rs485_flags''</tt>
|}
 
:'''Show UART flags'''
:{| class="wikitable"
|<tt>''./tty_rs485_flags /dev/ttySTM2''</tt>
|}
|}


:'''Set tty device to raw mode'''
:'''Set tty device to raw mode'''
:{| class="wikitable"
:{| class="wikitable"
|<tt>''stty -F /dev/ttySTM2 115200 cs8 raw -echo''</tt>
|<tt>''stty -F /dev/ttySTM2 115200 raw -echo -echoe''</tt>
|}
|}


:'''Send data with demo program'''
:'''Send data with demo program'''
:{| class="wikitable"
:{| class="wikitable"
|<tt>''echo -n -e "\n\rHallo RS485 Welt!" | ./tty_rs485_test /dev/ttySTM2''</tt>
|<tt>''echo -n -e "\n\rHallo RS485 Welt!" &brvbar; ./tty_rs485_test /dev/ttySTM2''</tt>
|}
|}


Line 69: Line 290:


:'''Download example source code'''
:'''Download example source code'''
:* [[media:Tty_rs485_test.zip | tty_rs485_test.c]]
:* [[media:tty_rs485_test_v1.1.zip | tty_rs485_test_v1.1.c & tty_rs485_flags_v1.0.c]]


=== CAN interface ===
=== CAN interface ===
Line 91: Line 312:
|<tt>''ip link set can0 down''</tt>
|<tt>''ip link set can0 down''</tt>
|}
|}
=== UART Interfaces ===
:{| class="wikitable" style="width: 400px"
||DHCOM UART 1 ||<tt>/dev/ttySTM0</tt>
|-
||DHCOM UART 2 ||<tt>/dev/ttySTM2</tt>
|-
||DHCOM UART 3 ||<tt>/dev/ttySTM1</tt>
|}
=== I2C Interfaces ===
:{| class="wikitable" style="width: 400px"
||DHCOM I2C 1||<tt>/dev/i2c-1</tt>
|-
||DHCOM I2C 2 ||<tt>/dev/i2c-0</tt>
|-
||On Module Devices ||<tt>/dev/i2c-2</tt>
|}
=== ADC/DAC Interfaces ===
:{|class="wikitable" style="text-align: center; width: 800px"
|-
! DHCOM Name !! SO-DIMM Pin# !! PDK2 Header !! Linux device !! sysfs in/out name !! STM32MP1 pin
|-
| AD0 || 8 || X18 Pin 8|| iio:device2 || in_voltage0_* || ANA0
|-
| AD1 || 6 || X18 Pin 6 || iio:device3 || in_voltage1_* || ANA1
|-
| AD2 || 4 || X18 Pin 4 || iio:device0 || out_voltage1_* || PA4_DAC_OUT1
|-
| AD3 || 2 || X18 Pin 2 || iio:device1 || out_voltage2_* || PA5_DAC_OUT2
|}
==== ADC inputs ====
:sysfs path
:{| class="wikitable"
|<tt>''/sys/bus/iio/devices/iio:device*''</tt>
|}
:Show offset and voltage scale
:{| class="wikitable"
|<tt>''cat in_voltage_scale''</tt>
|-
|<tt>''cat in_voltage_offset''</tt>
|}
: '''Notes:'''
:*Voltage = (RAW + OFFSET) * SCALE
:*Maximum input voltage = 2.9V (VDDA is connected to PMIC LDO1)
:Read analog value
:{| class="wikitable"
|<tt>''cat in_voltage*_raw''</tt>
|}
==== DAC outputs ====
:sysfs path
:{| class="wikitable"
|<tt>''/sys/bus/iio/devices/iio:device*''</tt>
|}
:Show output voltage scale
:{| class="wikitable"
|<tt>''cat out_voltage*_scale''</tt>
|}
:Enable DAC
:{| class="wikitable"
|<tt>''echo 0 > out_voltage*_powerdown''</tt>
|}
: '''Notes:'''
:*Voltage = RAW * SCALE
:*Maximum output voltage = 2.9V (VDDA is connected to PMIC LDO1)
:Set analog output value
:{| class="wikitable"
|<tt>''echo xxxx > out_voltage*_raw''</tt>
|}
== FAQ ==
==== How to connect to  WiFi network with WPA2 PSK? ====
:'''Establish connection'''
:{| class="wikitable"
|<tt>wpa_passphrase "SSID" >/etc/wpa_supplicant.conf</tt>
|}
:-> In the next step, please enter the password
:{| class="wikitable"
|<tt>ip link set wlan0 up</tt>
|-
|<tt>wpa_supplicant -i wlan0 -c /etc/wpa_supplicant.conf &</tt>
|-
|<tt>udhcpc -i wlan0</tt>
|}
:'''Disconnect'''
:{| class="wikitable"
|<tt>fg</tt>
|}
:-> Moves a background process  wpa_supplicant on your current Linux shell to the foreground. Then Press "Strg + C" to end the process.
:{| class="wikitable"
|<tt>ip link set wlan0 down</tt>
|}
==== How to set up WiFi AP? ====
:Create new AP configuration file
:{| class="wikitable"
|<tt>nano /etc/hostapd_myAP.conf</tt>
|}
:Insert the following to the file: (SSID = rsiwifi and default password = rsiTest1)
ctrl_interface=/var/run/hostapd
ctrl_interface_group=0
interface=wlan0
ssid=rsiwifi
hw_mode=g
channel=6
wpa=2
wpa_passphrase=rsiTest1
wpa_key_mgmt=WPA-PSK
:Configure the AP wlan0 interface or start DHCP server on it etc.
:{| class="wikitable"
|<tt>nano /etc/systemd/network/80-wlan0.network</tt>
|}
:Insert the following to the file:
[Match]
Path=platform-soc
[Network]
Address=11.11.11.11/24
DHCPServer=yes
:-> Reboot the system
:Start hostapd to start the AP:
:{| class="wikitable"
|<tt>hostapd -d hostapd_DRC02.conf >/dev/null &</tt>
|}
:'''Stop AP'''
:{| class="wikitable"
|<tt>fg</tt>
|}
:-> Moves a background process hostapd on your current Linux shell to the foreground. Then Press "Strg + C" to end the process.
:{| class="wikitable"
|<tt>ip link set wlan0 down</tt>
|}
==== How to enable WiFi/BT support, if missing? How to configure RSI mode (WiFi alone, Bluetooth, ...)? ====
:The needed sdmmc3 interface will be activated by the stm32mp15xx-dhcom-som.dtsi file. This is included by default with picoITX, PDK2 and DRC02 configuration.
:Next to this the kernel module is needed. The Yocto build instructions can be found at the following file:
:https://github.com/dh-electronics/meta-dhsom-stm32-bsp/blob/dunfell-3.1/conf/machine/dh-stm32mp1-dhcom-picoitx.conf
# Ship kernel modules
MACHINE_ESSENTIAL_EXTRA_RDEPENDS += " linux-firmware-rs9116 "
KERNEL_MODULE_AUTOLOAD += " rsi_sdio "
KERNEL_MODULE_PROBECONF += " rsi_sdio "
module_conf_rsi_sdio = "options rsi_sdio dev_oper_mode=1"
:If you are using a different root filesystem (compared to our Yocto configuration) please ensure, that the firmware files and the rsi_sdio.conf file are included in the filesystem:
:[[media:rsi_firmware.zip|rsi_firmware.zip]]
:* Copy the directory rsi to /lib/firmware/
:* Copy the file rsi_sdio.conf to /etc/modprobe.d/
:'''Note to DRC02:'''
:DRC02 default images with date Oct. 2021 or newer support WiFi/BT by an additional device tree overlay.
:To use the DTO, please add it to the U-Boot environment:
:{| class="wikitable"
|<tt>setenv loaddtos '#conf-stm32mp153c-dhcom-drc02.dtb#conf-stm32mp15xx-dhcom-drc02-overlay-wifi-rsi.dtbo'</tt>
|}
:'''RSI mode:'''
:By default, the RSI module is configured to WiFi alone mode with our Yocto image. The mode can be configured by rsi_sdio.conf file:
According to Linux kernel source, the dev_oper_mode has the following meaning:
linux-2.6$ git grep -n DEV_OPMODE_ drivers/net/wireless/rsi/ [...]
drivers/net/wireless/rsi/rsi_hal.h:21:#define DEV_OPMODE_WIFI_ALONE    1
drivers/net/wireless/rsi/rsi_hal.h:22:#define DEV_OPMODE_BT_ALONE      4
drivers/net/wireless/rsi/rsi_hal.h:23:#define DEV_OPMODE_BT_LE_ALONE    8
drivers/net/wireless/rsi/rsi_hal.h:24:#define DEV_OPMODE_BT_DUAL        12
drivers/net/wireless/rsi/rsi_hal.h:25:#define DEV_OPMODE_STA_BT        5
drivers/net/wireless/rsi/rsi_hal.h:26:#define DEV_OPMODE_STA_BT_LE      9
drivers/net/wireless/rsi/rsi_hal.h:27:#define DEV_OPMODE_STA_BT_DUAL    13
drivers/net/wireless/rsi/rsi_hal.h:28:#define DEV_OPMODE_AP_BT          6
drivers/net/wireless/rsi/rsi_hal.h:29:#define DEV_OPMODE_AP_BT_DUAL    14
:If you like to use Bluetooth alone mode, change dev_oper_mode to 12. Then you can use the standard hci commands. Start with 'hciconfig hci0 up' to activate the interface.
==== USB 1.1 problems: Custom board without USB 2.0 hub inbetween the MP1 USB host port? ====
And in that case, have a look at arch/arm/boot/dts/stm32mp15xx-dhcom-picoitx.dtsi and how the OHCI (!) is enabled there. And of course, make sure the kernel config options are enabled accordingly (like for the PicoITX machine)
{| class="wikitable" | style="width: 100%; color: #000000; background: #FFFFFF;" valign="top" |
|
<tt>meta-dhsom-stm32-bsp$ git grep OHCI</tt>
|}
{| class="wikitable" | style="width: 100%; color: #000000; background: #FFFFFF;" valign="top" |
|
<tt>recipes-kernel/linux/linux-stable/5.10/dh-stm32mp1-common/dh-stm32mp1-dhsom-common.cfg:CONFIG_USB_OHCI_HCD=y</tt><br/>
<tt>recipes-kernel/linux/linux-stable/5.10/dh-stm32mp1-common/dh-stm32mp1-dhsom-common.cfg:CONFIG_USB_OHCI_HCD_PLATFORM=y</tt>
|}
arch/arm/boot/dts/stm32mp15xx-dhcom-picoitx.dtsi snippet:
&usbh_ehci {
          phys = <&usbphyc_port0>;
          status = "okay";
};
&usbh_ohci { // <---------------- HERE
          phys = <&usbphyc_port0>;
          status = "okay";
};
&usbotg_hs {
          dr_mode = "otg";
          pinctrl-0 = <&usbotg_hs_pins_a>;
          pinctrl-names = "default";
          phy-names = "usb2-phy";
          phys = <&usbphyc_port1 0>;
          vbus-supply = <&vbus_otg>;
          status = "okay";
};
&usbphyc {
          status = "okay";
};
&usbphyc_port0 {
          phy-supply = <&vdd_usb>;
          vdda1v1-supply = <&reg11>;
          vdda1v8-supply = <&reg18>;
};
&usbphyc_port1 {
          phy-supply = <&vdd_usb>;
          vdda1v1-supply = <&reg11>;
          vdda1v8-supply = <&reg18>;
};
==== System stability or USB Host problems? ====
If a display with higher resolution and pixel clock > 48 MHz is used, then this can case USB host and/or system stability problems.
Workaround:
The OSPEEDR must be set to OSPEEDR = 1 for LCD_CLK and OSPEEDR = 0 for all other LTDC signals.
&pinctrl {
ltdc_pins_ customhmi: ltdc-dh-1 {
pins1 {
pinmux = <STM32_PINMUX('I', 14, AF14)>; /* LCD_CLK */
bias-disable;
drive-push-pull;
'''slew-rate = <1>;'''
};
pins2 {
pinmux = <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */
<STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */
                                  ...
<STM32_PINMUX('K',  6, AF14)>; /* LCD_B7 */
bias-disable;
drive-push-pull;
'''slew-rate = <0>;'''
};
};
ltdc_sleep_pins_ customhmi: ltdc-sleep-dh-1 {
pins {
pinmux = <STM32_PINMUX('I', 14, ANALOG)>, /* LCD_CLK */
                                  ...
<STM32_PINMUX('K',  6, ANALOG)>; /* LCD_B7 */
};
};
};
==== USB OTG: Custom board where the USB-OTG port is only used as host? ====
On the DHCOM standard, the second USB port of the STM32MP1 is usually an USB-OTG port. If you have a custom board where you want to use the USB-OTG port in host mode only, you should consider the following:
The USB-OTG controller on the STM32MP1, DWC2, does support host mode but is rather inefficient (in comparison to a dedicated USB host controller). The following block diagram shows, that it is possible on the STM32MP1 to alter the pinmuxing, so that the USB-OTG port is used with the USB Host controller of the STM32MP1 (instead of using the DWC2 OTG controller): 
    Host port#1: EHCI/OHCI controller _________ HS PHY port #1 (SoC balls D+/D- #1)
     
     
    Host port#2: EHCI/OHCI controller __
                                        \ 
                                        |_____ HS PHY port #2 (SoC balls D+/D- #2)
    DWC2 OTG controller_________________/|
                                        |
            UTIM switch__________________|
This change can be made in the device tree with disabling the DWC2 controller and adding the second usb_phyc port to the nodes of usbh_ehci and (if applicable) usbh_ohci. These nodes are usually in the .dtsi file of the board (e.g. for the PicoITX: arch/arm/boot/dts/stm32mp15xx-dhcom-picoitx.dtsi). Here a is snippet how this could look like:
&usbh_ehci {
          phys = <&usbphyc_port0>''', <&usbphyc_port1 1>'''; // <-------- HERE
          status = "okay";
};
&usbh_ohci {
          phys = <&usbphyc_port0>''', <&usbphyc_port1 1>'''; // <-------- HERE
          status = "okay";
};
&usbotg_hs {
          '''status = "disabled";''' // <-------- HERE
};
&usbphyc {
          status = "okay";
};
&usbphyc_port0 {
          phy-supply = <&vdd_usb>;
          vdda1v1-supply = <&reg11>;
          vdda1v8-supply = <&reg18>;
};
&usbphyc_port1 {
          phy-supply = <&vdd_usb>;
          vdda1v1-supply = <&reg11>;
          vdda1v8-supply = <&reg18>;
};
==== How to try QtWebengine ====
The QtWebengine is part of the DH default images.
Please stop the Weston desktop, before the start of the Browser.
Older images: "systemctl stop weston@root.service" 
Newer images: "systemctl stop weston.service"
How to start the Browser:
QT_QPA_PLATFORM=eglfs QT_QPA_EGLFS_ALWAYS_SET_MODE=1 QT_QPA_EGLFS_KMS_CONFIG=/etc/default/qt5-eglfs-kms.json qtwebengine-minimal http://YOUR-TEST-PAGE/ --no-sandbox
==== How is the Browser Perfomance on the STM32MP1? ====
[https://wiki.dh-electronics.com/index.php/STM32MP1_Browser_Performance STM32MP1 Browser Performance]
==== How to calibrate resistive touchscreens ====
{{:Calibration of resistive touchscreens}}

Latest revision as of 07:40, 20 October 2023

Linux virtual machine for development

Linux Kernel

How to build a Kernel

Get sources from Github

1. Start the Console on Linux
2. git clone https://github.com/dh-electronics/linux-stm32mp1.git --branch dev/5.4.69_dhsom
3. cd linux-stm32mp1

Configure and build the Device Tree + Kernel

4. ARCH=arm CROSS_COMPILE=/opt/gcc-arm-8.3-2019.03-x86_64-arm-linux-gnueabihf/bin/arm-linux-gnueabihf- make stm32mp1_dhsom_defconfig
5. ARCH=arm CROSS_COMPILE=/opt/gcc-arm-8.3-2019.03-x86_64-arm-linux-gnueabihf/bin/arm-linux-gnueabihf- make menuconfig (optional: If you want to add/remove Kernel features)
6. ARCH=arm CROSS_COMPILE=/opt/gcc-arm-8.3-2019.03-x86_64-arm-linux-gnueabihf/bin/arm-linux-gnueabihf- make dtbs
7. ARCH=arm CROSS_COMPILE=/opt/gcc-arm-8.3-2019.03-x86_64-arm-linux-gnueabihf/bin/arm-linux-gnueabihf- make zImage

Create the FIT-image with our script (Download link)

Interactive mode for selecting device trees Device trees are set as parameter

8. create_fitimage
Enter the numbers (space seperated) of the device trees to include (e.g. if you want to include the device tree for the PDK2 include the number of ./arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dtb (usually 3).
Enter the numbers (space seperated) of the device trees overlays to include (e.g. for the PDK2 enter the files which contain PDK2 (usually 8 9 10 11 12 13 14).

(Example is for the PDK2)
8. create_fitimage --dtb ./arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dtb --dtbo ./arch/arm/boot/dts/stm32mp157c-dhcom-pdk2-overlay-460-200-x11.dtbo,./arch/arm/boot/dts/stm32mp157c-dhcom-pdk2-overlay-497-200-x12.dtbo,./arch/arm/boot/dts/stm32mp157c-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh.dtbo,./arch/arm/boot/dts/stm32mp157c-dhcom-pdk2-overlay-531-100-x21.dtbo,./arch/arm/boot/dts/stm32mp157c-dhcom-pdk2-overlay-531-100-x22.dtbo,./arch/arm/boot/dts/stm32mp157c-dhcom-pdk2-overlay-560-200-x12.dtbo,./arch/arm/boot/dts/stm32mp157c-dhcom-pdk2-overlay-638-100-x12-rpi7inch.dtbo

DHSOM device tree structure

DHCOM and PDK2
--------------
* stm32mp15xx-dhcom-som.dtsi [1] -------------------------.
   [ STM32MP15xx based DHCOM SoM DT, common for all    ]   |
   [ variants of the SoC populated on the SoM.         ]   +--.
                                                           |  |
* stm32mp15xx-dhcom-pdk2.dtsi -----------------------------'  |
   [ STM32MP15xx based DHCOM PDK2 carrier board DT,    ]      |
   [ common for all of the PDK2 and SoM combinations.  ]      |
                                                              |
   * stm32mp157c-dhcom-pdk2.dts <-----------------------------'
     [ STM32MP157C based DHCOM SoM populated on PDK2   ]      :
     [ carrier board combined DT. This DT describes    ]      :
     [ specific combination of SoM populated on PDK2   ]      :
     [ carrier board.                                  ]      :
                                                              :
                                                              :
       Both common SoM and PDK2 DTs can be extended by DTOs   :
   .- - - - - - - - - - - - - - - - - - - - - - - - - - - - - '
   :   DTOs add additional bindings into base DTs at runtime.
   :
   :
   * stm32mp15xx-dhcom-pdk2-overlay-460-200-x11.dts
   : [ DH 460-200 FMC2 SRAM expansion card inserted into header X11.   ]
   :
   * stm32mp15xx-dhcom-pdk2-overlay-497-200-x12.dts
   : [ DH 497-200 7" 800x480 DPI TFT LCD and resistive touchscreen     ]
   : [ expansion card inserted into header X12.                        ]
   : [ This DT uses common DPI panel base DT, see [2].                 ]
   :
   * stm32mp15xx-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh.dts
   : [ DH 505-200 10" 1280x800 LVDS TFT LCD and capacitive             ]
   : [ touchscreen expansion card inserted into header X12.            ]
   : [ The panel interface is LVDS, connected to SoC via DPI-to-LVDS   ]
   : [ bridge chip OnSemi FIN3385.                                     ]
   : [ This DT uses common CH101 panel base DT, see [3].               ]
   :
   * stm32mp15xx-dhcom-pdk2-overlay-560-200-x12.dts
   : [ DH 560-200 7" 800x480 DPI TFT LCD and capacitive touchscreen    ]
   : [expansion card inserted into header X12.                         ]
   : [ This DT uses common DPI panel base DT, see [2].                 ]
   :
   * stm32mp15xx-dhcom-pdk2-overlay-638-100-x12-rpi7inch.dts
   : [ DH 638-100 adapter card connected to 7" 800x480 DSI TFT LCD and ]
   : [ capacitive touchscreen module, and inserted into header X12.    ]
   : [ The panel interface is DPI, connected to SoC via DSI-to-DPI     ]
   : [ bridge chip Toshiba TC358762.                                   ]
   : [ This DT uses common DPI panel base DT, see [2].                 ]
   :
   * stm32mp15xx-dhcom-pdk2-overlay-672-100-x18.dts
   : [ DH 672-100 CAN transceiver chip expansion board inserted into   ]
   : [ header X18.                                                     ]
   :
   * stm32mp15xx-dhcom-pdk2-overlay-531-100-x21.dts
   : [ DH 531-100 I2C and SPI EEPROM expansion board inserted into     ]
   : [ header X21.                                                     ]
   :
   * stm32mp15xx-dhcom-pdk2-overlay-531-100-x22.dts
     [ DH 531-100 I2C and SPI EEPROM expansion board inserted into     ]
     [ header X22.                                                     ]

DHCOM and PicoITX
-----------------
* stm32mp15xx-dhcom-som.dtsi -----------------------------.
   [ STM32MP15xx based DHCOM SoM DT, see also [1] above.]  |
                                                           +----.
                                                           |    |
* stm32mp15xx-dhcom-picoitx.dtsi --------------------------'    |
   [ STM32MP15xx based DHCOM PicoITX carrier board DT,  ]       |
   [ common for all of the PicoITX and SoM combinations.]       |
                                                                |
   * stm32mp157c-dhcom-picoitx.dts <----------------------------'
     [ STM32MP157C based DHCOM SoM populated on PicoITX ]       :
     [ carrier board combined DT. This DT describes     ]       :
     [ specific combination of SoM populated on PicoITX ]       :
     [ carrier board.                                   ]       :
                                                                :
                                                                :
       Both common SoM and PicoITX DTs can be extended by DTOs  :
   .- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - '
   :   DTOs add additional bindings into base DTs at runtime.
   :
   :
   * stm32mp15xx-dhcom-picoitx-overlay-548-200-x2-mi0700s4t-6.dts
   : [ DH 548-200 7" 800x480 DPI TFT LCD and resistive touchscreen   ]
   : [ expansion card inserted into header X2.                       ]
   :
   * stm32mp15xx-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh.dts
     [ DH 626-100 10" 1280x800 LVDS TFT LCD and capacitive           ]
     [ touchscreen expansion card inserted into header X2.           ]
     [ The panel interface is LVDS, connected to SoC via DPI-to-LVDS ]
     [ bridge chip OnSemi FIN3385.                                   ]
     [ This DT uses common CH101 panel base DT, see [3].             ]

DHCOM and DRC02
---------------
* stm32mp15xx-dhcom-som.dtsi -----------------------------.
   [ STM32MP15xx based DHCOM SoM DT, see also [1] above.]  |
                                                           +--.
                                                           |  |
* stm32mp15xx-dhcom-picoitx.dtsi --------------------------'  |
   [ STM32MP15xx based DHCOM DRC02 carrier board DT,  ]       |
   [ common for all of the DRC02 and SoM combinations.]       |
                                                              |
   * stm32mp153c-dhcom-picoitx.dts <--------------------------'
     [ STM32MP153C based DHCOM SoM populated on DRC02 ]       :
     [ carrier board combined DT. This DT describes   ]       :
     [ specific combination of SoM populated on DRC02 ]       :
     [ carrier board.                                 ]       :
                                                              :
                                                              :
       Both common SoM and DRC02 DTs can be extended by DTOs  :
   .- - - - - - - - - - - - - - - - - - - - - - - - - - - - - '
   :   DTOs add additional bindings into base DTs at runtime.
   :
   :
   * stm32mp15xx-dhcom-drc02-overlay-wifi-rsi.dts
     [ DH DHCOM DRC02 populated with DHCOM carrying RSI WiFi.        ]
     [ The carrier board MicroSD card is not available in this setup.]

DHCOM common DTSIs
------------------
   * stm32mp15xx-dhcom-overlay-panel-dpi-ch101olhlwh.dtsi [3]
     [ Common CH101 panel DT bindings used by all DHCOM systems.     ]
     [ This DT uses common DPI panel base DT, see [2].               ]
   * stm32mp15xx-dhcom-overlay-panel-dpi.dtsi [2]
     [ Common DPI panel DT bindings used by all DHCOM systems.       ]

Kernel Userspace Interfaces to Access Hardware

Control GPIOs

Show gpio definition in Linux
gpioinfo
Note:
gpiochip0 = STM port-A, gpiochip1 = STM port-B, ...
DHCOM Name: alt. DHCOM Name: SO-DIMM Pin# CPU Pad Name gpiod label:
GPIO A 154 PF3 DHCOM-A
GPIO B 156 PD6 DHCOM-B
GPIO C 162 PG0 DHCOM-C
GPIO D 163 PD12 DHCOM-D
GPIO E 164 PC6 DHCOM-E
GPIO F 165 PD11 DHCOM-F
GPIO G 167 PI0 DHCOM-G
GPIO H 173 PI2 DHCOM-H
GPIO I 175 PI3 DHCOM-I
GPIO J CIF HSYNC 74 PH8 DHCOM-J
GPIO K CIF PCLK 72 PA6 DHCOM-K
GPIO L CIF MCLK 70 PG8 DHCOM-L
GPIO M CIF VSYNC 68 PI5 DHCOM-M
GPIO N CIF D9 66 PH7 DHCOM-N
GPIO O CIF D8 64 PI1 DHCOM-O
GPIO P CIF D7 62 PE6 DHCOM-P
GPIO Q CIF D6 60 PB8 DHCOM-Q
GPIO R CIF D5 58 PI4 DHCOM-R
GPIO S CIF D4 56 PH14 DHCOM-S
GPIO T CIF D3 54 PH12 DHCOM-T
GPIO U CIF D2 52 PH11 DHCOM-U
GPIO V CIF D1 50 PH10 DHCOM-V
GPIO W CIF D0 48 PH9 DHCOM-W
INT HIGHEST PRIORITY 151 PI8 DHCOM-INT
Set state
gpioset $(gpiofind DHCOM-<#>)=0
gpioset $(gpiofind DHCOM-<#>)=1
or
gpioset gpiochip<port#> <pin#>=0
gpioset gpiochip<port#> <pin#>=1
Get state
gpioget $(gpiofind DHCOM-<#>)
or
gpioget gpiochip<port#> <pin#>

RS-485 (only picoITX or DRC02)

RS-485 device
DHCOM UART 2 /dev/ttySTM2
Compilation on target
gcc tty_rs485_test_v1.1.c -o tty_rs485_test
gcc tty_rs485_flags_v1.0.c -o tty_rs485_flags
Show UART flags
./tty_rs485_flags /dev/ttySTM2
Set tty device to raw mode
stty -F /dev/ttySTM2 115200 raw -echo -echoe
Send data with demo program
echo -n -e "\n\rHallo RS485 Welt!" ¦ ./tty_rs485_test /dev/ttySTM2
Receive data with demo program
./tty_rs485_test /dev/ttySTM2
Download example source code

CAN interface

Setup CAN interface with baudrate 500kbit/sec.
ip link set can0 up type can bitrate 500000
Start to listen on CAN port
candump can0
Send test message
cansend can0 100#11.2233.44556677.88
Deinitialize CAN port
ip link set can0 down

UART Interfaces

DHCOM UART 1 /dev/ttySTM0
DHCOM UART 2 /dev/ttySTM2
DHCOM UART 3 /dev/ttySTM1

I2C Interfaces

DHCOM I2C 1 /dev/i2c-1
DHCOM I2C 2 /dev/i2c-0
On Module Devices /dev/i2c-2

ADC/DAC Interfaces

DHCOM Name SO-DIMM Pin# PDK2 Header Linux device sysfs in/out name STM32MP1 pin
AD0 8 X18 Pin 8 iio:device2 in_voltage0_* ANA0
AD1 6 X18 Pin 6 iio:device3 in_voltage1_* ANA1
AD2 4 X18 Pin 4 iio:device0 out_voltage1_* PA4_DAC_OUT1
AD3 2 X18 Pin 2 iio:device1 out_voltage2_* PA5_DAC_OUT2

ADC inputs

sysfs path
/sys/bus/iio/devices/iio:device*
Show offset and voltage scale
cat in_voltage_scale
cat in_voltage_offset
Notes:
  • Voltage = (RAW + OFFSET) * SCALE
  • Maximum input voltage = 2.9V (VDDA is connected to PMIC LDO1)
Read analog value
cat in_voltage*_raw

DAC outputs

sysfs path
/sys/bus/iio/devices/iio:device*
Show output voltage scale
cat out_voltage*_scale
Enable DAC
echo 0 > out_voltage*_powerdown
Notes:
  • Voltage = RAW * SCALE
  • Maximum output voltage = 2.9V (VDDA is connected to PMIC LDO1)
Set analog output value
echo xxxx > out_voltage*_raw

FAQ

How to connect to WiFi network with WPA2 PSK?

Establish connection
wpa_passphrase "SSID" >/etc/wpa_supplicant.conf
-> In the next step, please enter the password
ip link set wlan0 up
wpa_supplicant -i wlan0 -c /etc/wpa_supplicant.conf &
udhcpc -i wlan0
Disconnect
fg
-> Moves a background process wpa_supplicant on your current Linux shell to the foreground. Then Press "Strg + C" to end the process.
ip link set wlan0 down

How to set up WiFi AP?

Create new AP configuration file
nano /etc/hostapd_myAP.conf
Insert the following to the file: (SSID = rsiwifi and default password = rsiTest1)
ctrl_interface=/var/run/hostapd
ctrl_interface_group=0
interface=wlan0
ssid=rsiwifi
hw_mode=g
channel=6
wpa=2
wpa_passphrase=rsiTest1
wpa_key_mgmt=WPA-PSK
Configure the AP wlan0 interface or start DHCP server on it etc.
nano /etc/systemd/network/80-wlan0.network
Insert the following to the file:
[Match]
Path=platform-soc

[Network]
Address=11.11.11.11/24
DHCPServer=yes
-> Reboot the system
Start hostapd to start the AP:
hostapd -d hostapd_DRC02.conf >/dev/null &
Stop AP
fg
-> Moves a background process hostapd on your current Linux shell to the foreground. Then Press "Strg + C" to end the process.
ip link set wlan0 down

How to enable WiFi/BT support, if missing? How to configure RSI mode (WiFi alone, Bluetooth, ...)?

The needed sdmmc3 interface will be activated by the stm32mp15xx-dhcom-som.dtsi file. This is included by default with picoITX, PDK2 and DRC02 configuration.
Next to this the kernel module is needed. The Yocto build instructions can be found at the following file:
https://github.com/dh-electronics/meta-dhsom-stm32-bsp/blob/dunfell-3.1/conf/machine/dh-stm32mp1-dhcom-picoitx.conf
# Ship kernel modules
MACHINE_ESSENTIAL_EXTRA_RDEPENDS += " linux-firmware-rs9116 "
KERNEL_MODULE_AUTOLOAD += " rsi_sdio "
KERNEL_MODULE_PROBECONF += " rsi_sdio "
module_conf_rsi_sdio = "options rsi_sdio dev_oper_mode=1"
If you are using a different root filesystem (compared to our Yocto configuration) please ensure, that the firmware files and the rsi_sdio.conf file are included in the filesystem:
rsi_firmware.zip
  • Copy the directory rsi to /lib/firmware/
  • Copy the file rsi_sdio.conf to /etc/modprobe.d/
Note to DRC02:
DRC02 default images with date Oct. 2021 or newer support WiFi/BT by an additional device tree overlay.
To use the DTO, please add it to the U-Boot environment:
setenv loaddtos '#conf-stm32mp153c-dhcom-drc02.dtb#conf-stm32mp15xx-dhcom-drc02-overlay-wifi-rsi.dtbo'
RSI mode:
By default, the RSI module is configured to WiFi alone mode with our Yocto image. The mode can be configured by rsi_sdio.conf file:
According to Linux kernel source, the dev_oper_mode has the following meaning:
linux-2.6$ git grep -n DEV_OPMODE_ drivers/net/wireless/rsi/ [...]
drivers/net/wireless/rsi/rsi_hal.h:21:#define DEV_OPMODE_WIFI_ALONE     1
drivers/net/wireless/rsi/rsi_hal.h:22:#define DEV_OPMODE_BT_ALONE       4
drivers/net/wireless/rsi/rsi_hal.h:23:#define DEV_OPMODE_BT_LE_ALONE    8
drivers/net/wireless/rsi/rsi_hal.h:24:#define DEV_OPMODE_BT_DUAL        12
drivers/net/wireless/rsi/rsi_hal.h:25:#define DEV_OPMODE_STA_BT         5
drivers/net/wireless/rsi/rsi_hal.h:26:#define DEV_OPMODE_STA_BT_LE      9
drivers/net/wireless/rsi/rsi_hal.h:27:#define DEV_OPMODE_STA_BT_DUAL    13
drivers/net/wireless/rsi/rsi_hal.h:28:#define DEV_OPMODE_AP_BT          6
drivers/net/wireless/rsi/rsi_hal.h:29:#define DEV_OPMODE_AP_BT_DUAL     14
If you like to use Bluetooth alone mode, change dev_oper_mode to 12. Then you can use the standard hci commands. Start with 'hciconfig hci0 up' to activate the interface.

USB 1.1 problems: Custom board without USB 2.0 hub inbetween the MP1 USB host port?

And in that case, have a look at arch/arm/boot/dts/stm32mp15xx-dhcom-picoitx.dtsi and how the OHCI (!) is enabled there. And of course, make sure the kernel config options are enabled accordingly (like for the PicoITX machine)

meta-dhsom-stm32-bsp$ git grep OHCI

recipes-kernel/linux/linux-stable/5.10/dh-stm32mp1-common/dh-stm32mp1-dhsom-common.cfg:CONFIG_USB_OHCI_HCD=y
recipes-kernel/linux/linux-stable/5.10/dh-stm32mp1-common/dh-stm32mp1-dhsom-common.cfg:CONFIG_USB_OHCI_HCD_PLATFORM=y

arch/arm/boot/dts/stm32mp15xx-dhcom-picoitx.dtsi snippet: 

&usbh_ehci {
         phys = <&usbphyc_port0>;
         status = "okay";
};

&usbh_ohci { // <---------------- HERE
         phys = <&usbphyc_port0>;
         status = "okay";
};

&usbotg_hs {
         dr_mode = "otg";
         pinctrl-0 = <&usbotg_hs_pins_a>;
         pinctrl-names = "default";
         phy-names = "usb2-phy";
         phys = <&usbphyc_port1 0>;
         vbus-supply = <&vbus_otg>;
         status = "okay";
};

&usbphyc {
         status = "okay";
};

&usbphyc_port0 {
         phy-supply = <&vdd_usb>;
         vdda1v1-supply = <&reg11>;
         vdda1v8-supply = <&reg18>;
};

&usbphyc_port1 {
         phy-supply = <&vdd_usb>;
         vdda1v1-supply = <&reg11>;
         vdda1v8-supply = <&reg18>;
};

System stability or USB Host problems?

If a display with higher resolution and pixel clock > 48 MHz is used, then this can case USB host and/or system stability problems.

Workaround: The OSPEEDR must be set to OSPEEDR = 1 for LCD_CLK and OSPEEDR = 0 for all other LTDC signals. 

&pinctrl {
	ltdc_pins_ customhmi: ltdc-dh-1 {
		pins1 {
			pinmux = <STM32_PINMUX('I', 14, AF14)>; /* LCD_CLK */
			bias-disable;
			drive-push-pull;
			slew-rate = <1>;
		};
		pins2 {
				pinmux = <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */
				 <STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */
                                 ...
				 <STM32_PINMUX('K',  6, AF14)>; /* LCD_B7 */
			bias-disable;
			drive-push-pull;
			slew-rate = <0>;
		};
	};
	
	ltdc_sleep_pins_ customhmi: ltdc-sleep-dh-1 {
		pins {
			pinmux = <STM32_PINMUX('I', 14, ANALOG)>, /* LCD_CLK */
                                 ...
				 <STM32_PINMUX('K',  6, ANALOG)>; /* LCD_B7 */
		};
	};	
};

USB OTG: Custom board where the USB-OTG port is only used as host?

On the DHCOM standard, the second USB port of the STM32MP1 is usually an USB-OTG port. If you have a custom board where you want to use the USB-OTG port in host mode only, you should consider the following:

The USB-OTG controller on the STM32MP1, DWC2, does support host mode but is rather inefficient (in comparison to a dedicated USB host controller). The following block diagram shows, that it is possible on the STM32MP1 to alter the pinmuxing, so that the USB-OTG port is used with the USB Host controller of the STM32MP1 (instead of using the DWC2 OTG controller): 

   Host port#1: EHCI/OHCI controller _________ HS PHY port #1 (SoC balls D+/D- #1)
      
      
   Host port#2: EHCI/OHCI controller __ 
                                        \   
                                        |_____ HS PHY port #2 (SoC balls D+/D- #2)
   DWC2 OTG controller_________________/|
                                        |
           UTIM switch__________________|

This change can be made in the device tree with disabling the DWC2 controller and adding the second usb_phyc port to the nodes of usbh_ehci and (if applicable) usbh_ohci. These nodes are usually in the .dtsi file of the board (e.g. for the PicoITX: arch/arm/boot/dts/stm32mp15xx-dhcom-picoitx.dtsi). Here a is snippet how this could look like: 

&usbh_ehci {
         phys = <&usbphyc_port0>, <&usbphyc_port1 1>; // <-------- HERE
         status = "okay";
};

&usbh_ohci { 
         phys = <&usbphyc_port0>, <&usbphyc_port1 1>; // <-------- HERE
         status = "okay";
};

&usbotg_hs {
         status = "disabled"; // <-------- HERE
};

&usbphyc {
         status = "okay";
};

&usbphyc_port0 {
         phy-supply = <&vdd_usb>;
         vdda1v1-supply = <&reg11>;
         vdda1v8-supply = <&reg18>;
};

&usbphyc_port1 {
         phy-supply = <&vdd_usb>;
         vdda1v1-supply = <&reg11>;
         vdda1v8-supply = <&reg18>;
};

How to try QtWebengine

The QtWebengine is part of the DH default images. Please stop the Weston desktop, before the start of the Browser. 

Older images: "systemctl stop weston@root.service"  
Newer images: "systemctl stop weston.service"

How to start the Browser: 

QT_QPA_PLATFORM=eglfs QT_QPA_EGLFS_ALWAYS_SET_MODE=1 QT_QPA_EGLFS_KMS_CONFIG=/etc/default/qt5-eglfs-kms.json qtwebengine-minimal http://YOUR-TEST-PAGE/ --no-sandbox

How is the Browser Perfomance on the STM32MP1?

STM32MP1 Browser Performance

How to calibrate resistive touchscreens

On devices with resistive touchscreens, the touchscreen has to be calibrated.

At our yocto images, we usually use libinput as library for handling input.

Prerequisites

  • Yocto packages weston, weston-init and weston-examples have to be installed inside the image.
  • The config file /etc/xdg/weston/weston.ini needs the following lines (to enable touchscreen calibration):
[libinput]
touchscreen_calibrator=true

After changing the configuration of weston, weston needs to be restarted:

systemctl restart weston

Steps for calibration

1. Get the touchscreen device name with weston-touch-calibrator

XDG_RUNTIME_DIR=/var/run/user/$(id -u weston) weston-touch-calibrator

Example result (bold part is needed for next steps):

device "/sys/devices/platform/soc/2100000.bus/21a8000.i2c/i2c-2/2-0049/input/input0/event0" - head "DPI-1"

2. Run weston-touch-calibrator on the device for starting the calibration. With the example part of the last result, the command looks like this (bold part is from the last result):

XDG_RUNTIME_DIR=/var/run/user/$(id -u weston) weston-touch-calibrator -v /sys/devices/platform/soc/2100000.bus/21a8000.i2c/i2c-2/2-0049/input/input0/event0

Now you press the highlighted points at the touchscreen to calibrate it. You will now get an output on the console like this (the important part is marked bold):

Calibration values: -0.001472 -1.081086 1.033880 -1.135099 0.000319 1.082698

3. To make the calibration permanent, you need to add a udev rule. Create the file /etc/udev/rules.d/touchscreen-cal.rules and use the calibration values there. With the result of the previous example, the file looks like this (bold part is the result of the last example): 

SUBSYSTEM=="input", KERNEL=="event[0-9]*", ENV{ID_INPUT_TOUCHSCREEN}=="1", ENV{LIBINPUT_CALIBRATION_MATRIX}="-0.001472 -1.081086 1.033880 -1.135099 0.000319 1.082698"
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