DHCOM STM32MP1 Linux: Difference between revisions

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== FAQ ==
== FAQ ==
==== '''How to enable WiFi/BT support if missing? How to configure RSI mode (WiFi alone, Bluetooth, ...)?''' ====
==== '''USB 1.1 problems: Custom board without USB 2.0 hub inbetween the MP1 USB host port?''' ====
==== '''USB 1.1 problems: Custom board without USB 2.0 hub inbetween the MP1 USB host port?''' ====
And in that case, have a look at arch/arm/boot/dts/stm32mp15xx-dhcom-picoitx.dtsi and how the OHCI (!) is enabled there. And of course, make sure the kernel config options are enabled accordingly (like for the PicoITX machine)
And in that case, have a look at arch/arm/boot/dts/stm32mp15xx-dhcom-picoitx.dtsi and how the OHCI (!) is enabled there. And of course, make sure the kernel config options are enabled accordingly (like for the PicoITX machine)

Revision as of 10:08, 16 September 2021

Linux virtual machine for development

Linux Kernel

How to build a Kernel

Get sources from Github

1. Start the Console on Linux
2. git clone https://github.com/dh-electronics/linux-stm32mp1.git --branch dev/5.4.69_dhsom
3. cd linux-stm32mp1

Configure and build the Device Tree + Kernel

4. ARCH=arm CROSS_COMPILE=/opt/gcc-arm-8.3-2019.03-x86_64-arm-linux-gnueabihf/bin/arm-linux-gnueabihf- make stm32mp1_dhsom_defconfig
5. ARCH=arm CROSS_COMPILE=/opt/gcc-arm-8.3-2019.03-x86_64-arm-linux-gnueabihf/bin/arm-linux-gnueabihf- make menuconfig (optional: If you want to add/remove Kernel features)
6. ARCH=arm CROSS_COMPILE=/opt/gcc-arm-8.3-2019.03-x86_64-arm-linux-gnueabihf/bin/arm-linux-gnueabihf- make dtbs
7. ARCH=arm CROSS_COMPILE=/opt/gcc-arm-8.3-2019.03-x86_64-arm-linux-gnueabihf/bin/arm-linux-gnueabihf- make zImage

Create the FIT-image with our script (Download link)

Interactive mode for selecting device trees Device trees are set as parameter

8. create_fitimage
Enter the numbers (space seperated) of the device trees to include (e.g. if you want to include the device tree for the PDK2 include the number of ./arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dtb (usually 3).
Enter the numbers (space seperated) of the device trees overlays to include (e.g. for the PDK2 enter the files which contain PDK2 (usually 8 9 10 11 12 13 14).

(Example is for the PDK2)
8. create_fitimage --dtb ./arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dtb --dtbo ./arch/arm/boot/dts/stm32mp157c-dhcom-pdk2-overlay-460-200-x11.dtbo,./arch/arm/boot/dts/stm32mp157c-dhcom-pdk2-overlay-497-200-x12.dtbo,./arch/arm/boot/dts/stm32mp157c-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh.dtbo,./arch/arm/boot/dts/stm32mp157c-dhcom-pdk2-overlay-531-100-x21.dtbo,./arch/arm/boot/dts/stm32mp157c-dhcom-pdk2-overlay-531-100-x22.dtbo,./arch/arm/boot/dts/stm32mp157c-dhcom-pdk2-overlay-560-200-x12.dtbo,./arch/arm/boot/dts/stm32mp157c-dhcom-pdk2-overlay-638-100-x12-rpi7inch.dtbo

Kernel Userspace Interfaces to Access Hardware

Control GPIOs

Show gpio definition in Linux
gpioinfo
Note:
gpiochip0 = STM port-A, gpiochip1 = STM port-B, ...
DHCOM Name: alt. DHCOM Name: SO-DIMM Pin# CPU Pad Name
GPIO A 154 PF3
GPIO B 156 PD6
GPIO C 162 PG0
GPIO D 163 PD12
GPIO E 164 PC6
GPIO F 165 PD11
GPIO G 167 PI0
GPIO H 173 PI2
GPIO I 175 PI3
GPIO J CIF HSYNC 74 PH8
GPIO K CIF PCLK 72 PA6
GPIO L CIF MCLK 70 PG8
GPIO M CIF VSYNC 68 PI5
GPIO N CIF D9 66 PH7
GPIO O CIF D8 64 PI1
GPIO P CIF D7 62 PE6
GPIO Q CIF D6 60 PB8
GPIO R CIF D5 58 PI4
GPIO S CIF D4 56 PH14
GPIO T CIF D3 54 PH12
GPIO U CIF D2 52 PH11
GPIO V CIF D1 50 PH10
GPIO W CIF D0 48 PH9
INT HIGHEST PRIORITY 151 PI8
Set state
gpioset $(gpiofind DHCOM-<#>)=0
gpioset $(gpiofind DHCOM-<#>)=1
or
gpioset gpiochip<port#> <pin#>=0
gpioset gpiochip<port#> <pin#>=1
Get state
gpioget $(gpiofind DHCOM-<#>)
or
gpioget gpiochip<port#> <pin#>

RS-485 on picoITX

RS-485 device
DHCOM UART 2 /dev/ttySTM2
Compilation on target
gcc tty_rs485_test_v1.1.c -o tty_rs485_test
gcc tty_rs485_flags_v1.0.c -o tty_rs485_flags
Show UART flags
./tty_rs485_flags /dev/ttySTM2
Set tty device to raw mode
stty -F /dev/ttySTM2 115200 raw -echo -echoe
Send data with demo program
echo -n -e "\n\rHallo RS485 Welt!" ¦ ./tty_rs485_test /dev/ttySTM2
Receive data with demo program
./tty_rs485_test /dev/ttySTM2
Download example source code

CAN interface

Setup CAN interface with baudrate 500kbit/sec.
ip link set can0 up type can bitrate 500000
Start to listen on CAN port
candump can0
Send test message
cansend can0 100#11.2233.44556677.88
Deinitialize CAN port
ip link set can0 down

UART Interfaces

DHCOM UART 1 /dev/ttySTM0
DHCOM UART 2 /dev/ttySTM2
DHCOM UART 3 /dev/ttySTM1

I2C Interfaces

DHCOM I2C 1 /dev/i2c-1
DHCOM I2C 2 /dev/i2c-0
On Module Devices /dev/i2c-2

FAQ

How to enable WiFi/BT support if missing? How to configure RSI mode (WiFi alone, Bluetooth, ...)?

USB 1.1 problems: Custom board without USB 2.0 hub inbetween the MP1 USB host port?

And in that case, have a look at arch/arm/boot/dts/stm32mp15xx-dhcom-picoitx.dtsi and how the OHCI (!) is enabled there. And of course, make sure the kernel config options are enabled accordingly (like for the PicoITX machine)

meta-dhsom-stm32-bsp$ git grep OHCI

recipes-kernel/linux/linux-stable/5.10/dh-stm32mp1-common/dh-stm32mp1-dhsom-common.cfg:CONFIG_USB_OHCI_HCD=y
recipes-kernel/linux/linux-stable/5.10/dh-stm32mp1-common/dh-stm32mp1-dhsom-common.cfg:CONFIG_USB_OHCI_HCD_PLATFORM=y

arch/arm/boot/dts/stm32mp15xx-dhcom-picoitx.dtsi snippet: 

&usbh_ehci {
         phys = <&usbphyc_port0>;
         status = "okay";
};

&usbh_ohci { // <---------------- HERE
         phys = <&usbphyc_port0>;
         status = "okay";
};

&usbotg_hs {
         dr_mode = "otg";
         pinctrl-0 = <&usbotg_hs_pins_a>;
         pinctrl-names = "default";
         phy-names = "usb2-phy";
         phys = <&usbphyc_port1 0>;
         vbus-supply = <&vbus_otg>;
         status = "okay";
};

&usbphyc {
         status = "okay";
};

&usbphyc_port0 {
         phy-supply = <&vdd_usb>;
         vdda1v1-supply = <&reg11>;
         vdda1v8-supply = <&reg18>;
};

&usbphyc_port1 {
         phy-supply = <&vdd_usb>;
         vdda1v1-supply = <&reg11>;
         vdda1v8-supply = <&reg18>;
};

System stability or USB Host problems?

If a display with higher resolution and pixel clock > 48 MHz is used, then this can case USB host and/or system stability problems.

Workaround: The OSPEEDR must be set to OSPEEDR = 1 for LCD_CLK and OSPEEDR = 0 for all other LTDC signals. 

&pinctrl {
	ltdc_pins_ customhmi: ltdc-dh-1 {
		pins1 {
			pinmux = <STM32_PINMUX('I', 14, AF14)>; /* LCD_CLK */
			bias-disable;
			drive-push-pull;
			slew-rate = <1>;
		};
		pins2 {
				pinmux = <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */
				 <STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */
                                 ...
				 <STM32_PINMUX('K',  6, AF14)>; /* LCD_B7 */
			bias-disable;
			drive-push-pull;
			slew-rate = <0>;
		};
	};
	
	ltdc_sleep_pins_ customhmi: ltdc-sleep-dh-1 {
		pins {
			pinmux = <STM32_PINMUX('I', 14, ANALOG)>, /* LCD_CLK */
                                 ...
				 <STM32_PINMUX('K',  6, ANALOG)>; /* LCD_B7 */
		};
	};	
};

USB OTG: Custom board where the USB-OTG port is only used as host?

On the DHCOM standard, the second USB port of the STM32MP1 is usually an USB-OTG port. If you have a custom board where you want to use the USB-OTG port in host mode only, you should consider the following:

The USB-OTG controller on the STM32MP1, DWC2, does support host mode but is rather inefficient (in comparison to a dedicated USB host controller). The following block diagram shows, that it is possible on the STM32MP1 to alter the pinmuxing, so that the USB-OTG port is used with the USB Host controller of the STM32MP1 (instead of using the DWC2 OTG controller): 

   Host port#1: EHCI/OHCI controller _________ HS PHY port #1 (SoC balls D+/D- #1)
      
      
   Host port#2: EHCI/OHCI controller __ 
                                        \   
                                        |_____ HS PHY port #2 (SoC balls D+/D- #2)
   DWC2 OTG controller_________________/|
                                        |
           UTIM switch__________________|

This change can be made in the device tree with disabling the DWC2 controller and adding the second usb_phyc port to the nodes of usbh_ehci and (if applicable) usbh_ohci. These nodes are usually in the .dtsi file of the board (e.g. for the PicoITX: arch/arm/boot/dts/stm32mp15xx-dhcom-picoitx.dtsi). Here a is snippet how this could look like: 

&usbh_ehci {
         phys = <&usbphyc_port0>, <&usbphyc_port1 1>; // <-------- HERE
         status = "okay";
};

&usbh_ohci { 
         phys = <&usbphyc_port0>, <&usbphyc_port1 1>; // <-------- HERE
         status = "okay";
};

&usbotg_hs {
         status = "disabled"; // <-------- HERE
};

&usbphyc {
         status = "okay";
};

&usbphyc_port0 {
         phy-supply = <&vdd_usb>;
         vdda1v1-supply = <&reg11>;
         vdda1v8-supply = <&reg18>;
};

&usbphyc_port1 {
         phy-supply = <&vdd_usb>;
         vdda1v1-supply = <&reg11>;
         vdda1v8-supply = <&reg18>;
};

How to try QtWebengine

The QtWebengine is part of the DH default images. Please stop the Weston desktop, before the start of the Browser. 

Older images: "systemctl stop weston@root.service"  
Newer images: "systemctl stop weston.service"

How to start the Browser: 

QT_QPA_PLATFORM=eglfs QT_QPA_EGLFS_ALWAYS_SET_MODE=1 QT_QPA_EGLFS_KMS_CONFIG=/etc/default/qt5-eglfs-kms.json qtwebengine-minimal http://YOUR-TEST-PAGE/ --no-sandbox

How is the Browser Perfomance on the STM32MP1?

STM32MP1 Browser Performance

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